summaryrefslogtreecommitdiff
path: root/src/vendorcode
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-01 19:23:35 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-10-05 13:23:27 +0000
commit0e1ea279d025887c6904b4bb559c7165b44c6dec (patch)
tree61e6532864340fed66237883e70f80dcddb251e6 /src/vendorcode
parent6287a69530133b63946e5c30b07a3c29fc3a25d9 (diff)
downloadcoreboot-0e1ea279d025887c6904b4bb559c7165b44c6dec.tar.xz
AGESA vendorcode: Add ENABLE_MRC_CACHE option
When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/agesa/common/agesa-entry-cfg.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index 0f72fe8c51..6602c99d49 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -24,7 +24,9 @@
#define AGESA_ENTRY_INIT_MID TRUE
#define AGESA_ENTRY_INIT_LATE TRUE
-#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_S3SAVE \
+ (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \
+ IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
#endif