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| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-28 10:26:31 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-09 13:19:48 +0100 |
| commit | 3cbf8d955f48fc39d5b3087934cbc5739ba07c5a (patch) | |
| tree | 5a312e76bbc0d2045d089187baffdcb7b7503e0c /src/vendorcode | |
| parent | 88b28ada69d032faf37753f0595658d507859d4a (diff) | |
| download | coreboot-3cbf8d955f48fc39d5b3087934cbc5739ba07c5a.tar.xz | |
chromeos: Remove CONFIG_VBNV_SIZE variable
The VBNV region size is determined by vboot and is not really
configurable. Only the CMOS implementation defined this config
variable so switch it to use VBNV_BLOCK_SIZE defined by vboot
in vbnv_layout.h instead.
This requires updating the broadwell/skylake cmos reset functions
to use the right constant.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell
Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d
Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324520
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13598
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/google/chromeos/Kconfig | 8 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/acpi/chromeos.asl | 4 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/vbnv_cmos.c | 4 |
3 files changed, 5 insertions, 11 deletions
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a7219bd2c1..79d6918e96 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -44,14 +44,6 @@ config VBNV_OFFSET CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC. -config VBNV_SIZE - hex - default 0x10 - depends on PC80_SYSTEM - help - CMOS storage size for VbNv data. This value must match cmos.layout - in the mainboard directory. - config CHROMEOS_VBNV_CMOS bool "Vboot non-volatile storage in CMOS." default n diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 5b2a26e93e..66ebbc1819 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <vendorcode/google/chromeos/vbnv_layout.h> + Device (CRHW) { Name(_HID, EISAID("GGL0001")) @@ -70,7 +72,7 @@ Device (CRHW) // See src/vendorcode/google/chromeos/Kconfig // for the definition of these: CONFIG_VBNV_OFFSET, - CONFIG_VBNV_SIZE + VBNV_BLOCK_SIZE }) Return(VNBV) } diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c index ddcb765fc7..e0d7ba1ea3 100644 --- a/src/vendorcode/google/chromeos/vbnv_cmos.c +++ b/src/vendorcode/google/chromeos/vbnv_cmos.c @@ -22,7 +22,7 @@ void read_vbnv_cmos(uint8_t *vbnv_copy) { int i; - for (i = 0; i < CONFIG_VBNV_SIZE; i++) + for (i = 0; i < VBNV_BLOCK_SIZE; i++) vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); } @@ -30,6 +30,6 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy) { int i; - for (i = 0; i < CONFIG_VBNV_SIZE; i++) + for (i = 0; i < VBNV_BLOCK_SIZE; i++) cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i); } |