src: Typo fix (cosmetic)

Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29196
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 8 insertions, 8 deletions

diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
index ba4d4e7893..2f4e0989b2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
@@ -115,7 +115,7 @@ F12IsCpbSupported (
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
  *
  * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
  *
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
index c7efe43532..6d28bfe5cb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
@@ -113,7 +113,7 @@ F15TnIsCpbSupported (
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
  *
  * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
  *
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
index 77f0b65ea1..1660c493ee 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
@@ -85,7 +85,7 @@ STATIC CONST UINT16 ROMDATA MmioBaseLimitHiRegOffset[MMIO_REG_PAIR_NUM] = {0x180
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * BSC entry point for for adding MMIO map
+ * BSC entry point for adding MMIO map
  *
  * program MMIO base/limit registers
  *
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
index db00c58e95..8d2fa344cb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
@@ -141,7 +141,7 @@ F16KbIsCpbSupported (
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
  *
  * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
  *
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
index cf1d0d8ee9..714f970d78 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -85,7 +85,7 @@ STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * BSC entry point for for adding MMIO map
+ * BSC entry point for adding MMIO map
  *
  * program MMIO base/limit registers
  *
diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
index 192a8a9194..0fcc180da8 100644
--- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
+++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
@@ -3295,7 +3295,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
         mem_size_mbytes *= 2;
     }
 
-    /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm.
+    /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm.
     ** This makes later calculations simpler, as a variety of CSRs use this layout.
     ** This init needs to be updated for dual configs (ie non-identical DIMMs).
     ** Bit 0 = dimm0, rank 0
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 12c6e4413c..d03a844037 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -2978,8 +2978,8 @@ typedef struct {
 **/
   UINT8                       ThreeStrikeCounterDisable;
 
-/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
-  Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT
+  Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       HwpInterruptControl;