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| author | Zheng Bao <fishbaozi@gmail.com> | 2012-11-27 18:08:53 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-11-27 11:03:52 +0100 |
| commit | b8117b062266eda6b8ac9a8b60881a99f0323a48 (patch) | |
| tree | c89c3f217e8e6c93a468876600e2993fe5ae3af0 /src/vendorcode | |
| parent | 1a5301dd3373e7def334fc34787f79073f49029a (diff) | |
| download | coreboot-b8117b062266eda6b8ac9a8b60881a99f0323a48.tar.xz | |
SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
For SST chips, the Write-Status-Register instruction must be
executed immediately after the execution of the
Enable-Write-Status-Register instruction, instead of Write-Enable.
Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode')
0 files changed, 0 insertions, 0 deletions