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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-05-22 06:16:15 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-14 20:38:49 +0200
commite93fe2344066e7471e82dacdaa53c9ed9a9b38e3 (patch)
treed49f392a2fc1b7370ba2d32bb407870e19317818 /src/vendorcode
parentcd30951e3243b1d67c36408aa94760955d9e4503 (diff)
downloadcoreboot-e93fe2344066e7471e82dacdaa53c9ed9a9b38e3.tar.xz
amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.c
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5802 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
index c2f93724f8..dc0903825e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -290,7 +290,7 @@ MemTDIMMPresence3 (
// as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will
// be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks.
//
- if (ChannelPtr->LrDimmPresent |= DimmMask) {
+ if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) {
//
// LRDIMM Physical Ranks
//
@@ -320,7 +320,7 @@ MemTDIMMPresence3 (
//
// Double Addr bus load value for dual rank DIMMs (Unless LRDIMM)
//
- if ( ((ChannelPtr->LrDimmPresent |= DimmMask) == 0) && (Value8 == 2) ) {
+ if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) {
Devwidth = Devwidth << 1;
}
//