diff options
| author | York Yang <york.yang@intel.com> | 2015-07-07 11:09:02 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-21 22:32:23 +0200 |
| commit | f226a4d41db5ab314200206e7cb8731f022a14a6 (patch) | |
| tree | 8f1436b87d1644a92fd3fde74f63e40ec11bb9c4 /src/vendorcode | |
| parent | d9c7a7b4dadc088c49a5668b13bb74fc6eea8079 (diff) | |
| download | coreboot-f226a4d41db5ab314200206e7cb8731f022a14a6.tar.xz | |
intel/fsp_baytrail: Support Baytrail FSP Gold4 release
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION
structure to include these new PCD options and initialized the setting
when given in devicetree.cb.
Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/10838
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/vendorcode')
| -rwxr-xr-x | src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h index 02de3cbd1c..76f7ce7b8a 100755 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -97,7 +97,12 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ UINT8 IgdRenderStandby; /* Offset 0x004E */ UINT8 TxeUmaEnable; /* Offset 0x004F */ - UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */ + UINT8 PcdOsSelection; /* Offset 0x0050 */ + UINT8 PcdEMMC45DDR50Enabled; /* Offset 0x0051 */ + UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */ + UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */ + UINT8 PcdEnableIgd; /* Offset 0x0054 */ + UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */ MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION; |