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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-23 17:17:47 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-03-31 18:07:40 +0000 |
| commit | 3e666898cd99f4e15a39e360bb594d499e738b2d (patch) | |
| tree | 3d30525f11bae4ad400b565e184451c0cc31b420 /src/vendorcode | |
| parent | 45808399fc04e7c623af6ee1e7c7686fab09e790 (diff) | |
| download | coreboot-3e666898cd99f4e15a39e360bb594d499e738b2d.tar.xz | |
vendorcode/intel/fsp: Update FSP header for Tiger Lake
Update FSPM header to include DisableDimmCh Upds for Tiger Lake
platform version 2457.
BUG=b:152000235
BRANCH=none
TEST="Build and Boot on Ripto/Volteer"
Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 44 |
1 files changed, 38 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 9bc1a409c7..b27514c644 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -356,9 +356,41 @@ typedef struct { **/ UINT8 RMT; -/** Offset 0x0194 - Reserved +/** Offset 0x0194 - DisableDimmCh0 **/ - UINT8 Reserved8[10]; + UINT8 DisableDimmCh0; + +/** Offset 0x0195 - DisableDimmCh1 +**/ + UINT8 DisableDimmCh1; + +/** Offset 0x0196 - DisableDimmCh2 +**/ + UINT8 DisableDimmCh2; + +/** Offset 0x0197 - DisableDimmCh3 +**/ + UINT8 DisableDimmCh3; + +/** Offset 0x0198 - DisableDimmCh4 +**/ + UINT8 DisableDimmCh4; + +/** Offset 0x0199 - DisableDimmCh5 +**/ + UINT8 DisableDimmCh5; + +/** Offset 0x019A - DisableDimmCh6 +**/ + UINT8 DisableDimmCh6; + +/** Offset 0x019B - DisableDimmCh7 +**/ + UINT8 DisableDimmCh7; + +/** Offset 0x019C - Reserved +**/ + UINT8 Reserved8[2]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -861,7 +893,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved38[355]; + UINT8 Reserved38[315]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -880,11 +912,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x08D8 +/** Offset 0x08B0 **/ - UINT8 UnusedUpdSpace24[6]; + UINT8 UnusedUpdSpace23[6]; -/** Offset 0x08DE +/** Offset 0x08B6 **/ UINT16 UpdTerminator; } FSPM_UPD; |