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| author | Piotr Kleinschmidt <piotr.kleins@gmail.com> | 2019-10-09 11:47:03 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-02-06 09:21:48 +0000 |
| commit | 7354605f869b60a9f3bf3495dee4ccdceb0da0a4 (patch) | |
| tree | 026d0b56982bda8eedf839d5d2bd91caa59838bc /src/vendorcode | |
| parent | eae254efb324e89d30d0f6abd3e40d6e951abba9 (diff) | |
| download | coreboot-7354605f869b60a9f3bf3495dee4ccdceb0da0a4.tar.xz | |
mb/pcengines/apu2: use AGESA 1.0.0.4 with adjusted AGESA header
PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA
1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly
utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which
is compatible with AGESA 1.0.0.4 version.
Cut out the changes introduced in CB:11225 exclusively for apu2 board.
TEST=boot PC Engines apu2 and launch Debian Linux
Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/amd/pi/00730F01/AGESA.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h index c25b631cb2..5a3ee5b9f6 100644 --- a/src/vendorcode/amd/pi/00730F01/AGESA.h +++ b/src/vendorcode/amd/pi/00730F01/AGESA.h @@ -775,6 +775,7 @@ typedef enum { DP_VS_0_4V_9_5DB = 0x18 ///< 0x18 } DP_FIXED_VOLT_SWING_TYPE; +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) /// Alternative DRAM MAC typedef enum { MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC @@ -785,6 +786,7 @@ typedef enum { MAC_300k, ///< Assign 5 to 300k MAC_200k, ///< Assign 6 to 200k } DRAM_MAXIMUM_ACTIVATE_COUNT; +#endif // Macro for statically initializing various structures #define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} @@ -1547,7 +1549,9 @@ typedef struct _CH_TIMING_STRUCT { ///< 667 (MHz) ///< 800 (MHz) ///< and so on... +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) OUT UINT8 Mac; ///< Maximum Activate Count +#endif OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) OUT UINT8 Trcd; ///< DCT Trcd (busclocks) OUT UINT8 Trp; ///< DCT Trp (busclocks) @@ -1803,6 +1807,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) // Dram Mac Default IN UINT8 DramMacDefault; ///< Default Maximum Activate Count @@ -1818,6 +1823,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} // Extended temperature range +#endif // Online Spare IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. @@ -2721,8 +2727,10 @@ typedef struct { IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range +#endif IN UINT32 CfgPowerDownMode; ///< Power Down Mode. IN BOOLEAN CfgOnlineSpare; ///< Online Spare. IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. |