summaryrefslogtreecommitdiff
path: root/src/vendorcode
diff options
context:
space:
mode:
authorBalaji Manigandan B <balaji.manigandan@intel.com>2017-09-22 14:27:56 +0530
committerMartin Roth <martinroth@google.com>2017-10-05 17:45:46 +0000
commitbd55c02a2398e2ce95cb06ff9f1e3fb1c20d0ab8 (patch)
tree17496aca51e0b349ac9816ba9fb27102219cc1ea /src/vendorcode
parent53b8a82e72b74e7598c5344597e014cd5c6fb49e (diff)
downloadcoreboot-bd55c02a2398e2ce95cb06ff9f1e3fb1c20d0ab8.tar.xz
vendor/intel/skykabylake: Update FSP header files to version 2.7.2
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h12
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h45
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h111
3 files changed, 123 insertions, 45 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index 1916e4e1c0..f3aa4c85c6 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -844,7 +844,7 @@ typedef struct {
/** Offset 0x02E3 - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
- lower than the core ratio.<b>0: Disable</b>; 1: Enable.
+ lower than the core ratio. 0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 RingDownBin;
@@ -1255,9 +1255,15 @@ typedef struct {
**/
UINT8 Avx3RatioOffset;
-/** Offset 0x051B
+/** Offset 0x051B - Ask MRC to clear memory content
+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x051C
**/
- UINT8 ReservedFspmUpd[5];
+ UINT8 ReservedFspmUpd[4];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index b3c7698857..f4f4badf47 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -167,7 +167,7 @@ typedef struct {
/** Offset 0x0036 - Flash Configuration Lock Down
Enable/disable flash lock down. If platform decides to skip this programming, it
- must lock SPI flash register before end of post.
+ must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
$EN_DIS
**/
UINT8 SpiFlashCfgLockDown;
@@ -484,7 +484,7 @@ typedef struct {
/** Offset 0x020C - PCIe DeEmphasis control per root port
0: -6dB, 1(Default): -3.5dB
- 0:Disable, 2:L1
+ 0:-6dB, 1:-3.5dB
**/
UINT8 PegDeEmphasis[3];
@@ -2060,9 +2060,15 @@ typedef struct {
**/
UINT8 MeUnconfigIsValid;
-/** Offset 0x077A
+/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
+**/
+ UINT8 IslVrCmd;
+
+/** Offset 0x077B
**/
- UINT8 ReservedFspsUpd[6];
+ UINT8 ReservedFspsUpd[5];
} FSP_S_CONFIG;
/** Fsp S Test Configuration
@@ -2107,7 +2113,7 @@ typedef struct {
UINT8 DmiIot;
/** Offset 0x0789 - PEG Max Payload size per root port
- 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B
+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
**/
UINT8 PegMaxPayload[3];
@@ -2520,25 +2526,25 @@ typedef struct {
/** Offset 0x07DA - Enable or Disable Package C-State Demotion
Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
(Auto: Enabled for Skylake; Disabled for Kabylake)
- $EN_DIS
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 PkgCStateDemotion;
/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
(Auto: Enabled for Skylake; Disabled for Kabylake)
- $EN_DIS
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 PkgCStateUnDemotion;
/** Offset 0x07DC - Enable or Disable CState-Pre wake
- Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
/** Offset 0x07DD - Enable or Disable TimedMwait Support.
- Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
@@ -2606,7 +2612,7 @@ typedef struct {
/** Offset 0x07E8 - Configuration for boot TDP selection
Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
- Up;0xFF : Deactivate
+ Up; 0xFF: Deactivate
0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
**/
UINT8 ConfigTdpLevel;
@@ -2632,12 +2638,14 @@ typedef struct {
UINT16 StateRatio[40];
/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
- Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF
+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,
+ Default is 0x4E, Server Platform is 0x4B
**/
UINT16 CstateLatencyControl0Irtl;
/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,
+ Default is 0x76, Server Platform is 0x6B
**/
UINT16 CstateLatencyControl1Irtl;
@@ -2783,11 +2791,18 @@ typedef struct {
**/
UINT8 EightCoreRatioLimit;
-/** Offset 0x0888 - ReservedCpuPostMemTest
+/** Offset 0x0888 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents Three
+ Strike counter from incrementing; <b>0: False</b>; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0889 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
- UINT8 ReservedCpuPostMemTest[2];
+ UINT8 ReservedCpuPostMemTest[1];
/** Offset 0x088A - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values
@@ -2923,7 +2938,7 @@ typedef struct {
UINT8 PchPmDisableEnergyReport;
/** Offset 0x0A2F - PCH Pm Pmc Read Disable
- When set to true, this bit disallows host reads to PMC XRAM.
+ Deprecated
$EN_DIS
**/
UINT8 PchPmPmcReadDisable;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
index 8dc2db9437..248b4d5ef1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
@@ -53,6 +53,25 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
#define B_RANK2_PRS BIT4
#define B_RANK3_PRS BIT5
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
///
/// Defines taken from MRC so avoid having to include MrcInterface.h
///
@@ -122,7 +141,7 @@ typedef struct {
#define MRC_DDR_TYPE_UNKNOWN 3
#endif
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
//
@@ -151,64 +170,102 @@ typedef struct {
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
} MRC_CH_TIMING;
+typedef struct {
+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
+} MRC_TA_TIMING;
+
///
/// Memory SMBIOS & OC Memory Data Hob
///
typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
} CONTROLLER_INFO;
typedef struct {
UINT8 Revision;
- UINT16 DataWidth;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
- UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
- UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE_NUM];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT32 PrmrrBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
#pragma pack (pop)
#endif // _MEM_INFO_HOB_H_