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authorStefan Reinauer <reinauer@chromium.org>2011-11-02 16:12:34 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 01:07:49 +0200
commit00093a81d3f54c72215d9f402c3f88880da89a81 (patch)
tree9e36867db1a94d195fdf69be11c3e847800ab82c /src
parent1afe51af83ad0beb3f0ace1085524b327ecff7c6 (diff)
downloadcoreboot-00093a81d3f54c72215d9f402c3f88880da89a81.tar.xz
Add an option to keep the ROM cached after romstage
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/include/arch/acpi.h4
-rw-r--r--src/cpu/x86/Kconfig4
-rw-r--r--src/cpu/x86/lapic/Makefile.inc1
-rw-r--r--src/cpu/x86/lapic/boot_cpu.c3
-rw-r--r--src/cpu/x86/mtrr/mtrr.c14
-rw-r--r--src/include/cpu/x86/lapic.h7
6 files changed, 26 insertions, 7 deletions
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d5ab..504d71b4f5 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void);
void acpi_jump_to_wakeup(void *wakeup_addr);
int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
#endif
/* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,6 +435,7 @@ void generate_cpu_entries(void);
#else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
#endif
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index d2809f8fe8..68946227b9 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -40,4 +40,6 @@ config LOGICAL_CPUS
bool
default y
-
+config CACHE_ROM
+ bool
+ default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956a9a..f3fcadc0a7 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0883..0fb9d5d35c 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
{
int bsp;
msr_t msr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d4c7..9015ad4d97 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <arch/acpi.h>
#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
};
-
void enable_fixed_mtrr(void)
{
msr_t msr;
@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
while(var_state.reg < MTRRS) {
set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
}
+
+#if CONFIG_CACHE_ROM
+ /* Enable Caching and speculative Reads for the
+ * complete ROM now that we actually have RAM.
+ */
+ if (boot_cpu() && (acpi_slp_type != 3)) {
+ set_var_mtrr(7, (4096-4)*1024, 4*1024,
+ MTRR_TYPE_WRPROT, address_bits);
+ }
+#endif
+
printk(BIOS_SPEW, "call enable_var_mtrr()\n");
enable_var_mtrr();
printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 68608edab1..2215ec7ee5 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -27,8 +27,6 @@ static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
}
-
-
static inline void enable_lapic(void)
{
@@ -53,7 +51,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
return lapic_read(LAPIC_ID) >> 24;
}
-
+#ifndef __ROMCC__
#if CONFIG_AP_IN_SIPI_WAIT != 1
/* If we need to go back to sipi wait, we use the long non-inlined version of
* this function in lapic_cpu_init.c
@@ -156,4 +154,7 @@ int start_cpu(struct device *cpu);
#endif /* !__PRE_RAM__ */
+int boot_cpu(void);
+#endif
+
#endif /* CPU_X86_LAPIC_H */