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authorAaron Durbin <adurbin@chromium.org>2020-05-27 08:31:26 -0600
committerAaron Durbin <adurbin@chromium.org>2020-05-28 19:38:33 +0000
commit0013623b7c976b8f79778cecf3f146dc7aeab6e9 (patch)
tree9cd19358a84a2ffe1c103f8186def1097be6d959 /src
parenta85febcb1cfd31bd4d27e955fc2bcf9f8ef16cd5 (diff)
downloadcoreboot-0013623b7c976b8f79778cecf3f146dc7aeab6e9.tar.xz
mb/google/dragonegg: remove abandoned project
Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dragonegg/Kconfig75
-rw-r--r--src/mainboard/google/dragonegg/Kconfig.name5
-rw-r--r--src/mainboard/google/dragonegg/Makefile.inc23
-rw-r--r--src/mainboard/google/dragonegg/board_info.txt6
-rw-r--r--src/mainboard/google/dragonegg/bootblock.c15
-rw-r--r--src/mainboard/google/dragonegg/chromeos.c37
-rw-r--r--src/mainboard/google/dragonegg/chromeos.fmd44
-rw-r--r--src/mainboard/google/dragonegg/dsdt.asl47
-rw-r--r--src/mainboard/google/dragonegg/ec.c17
-rw-r--r--src/mainboard/google/dragonegg/mainboard.c31
-rw-r--r--src/mainboard/google/dragonegg/romstage_fsp_params.c73
-rw-r--r--src/mainboard/google/dragonegg/smihandler.c26
-rw-r--r--src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex32
-rw-r--r--src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex32
-rw-r--r--src/mainboard/google/dragonegg/spd/Makefile.inc26
-rw-r--r--src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex32
-rw-r--r--src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex32
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc7
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb329
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/gpio.c87
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h69
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h27
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h30
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/memory.c57
-rw-r--r--src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h8
-rw-r--r--src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h8
26 files changed, 0 insertions, 1175 deletions
diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig
deleted file mode 100644
index 550d83a7df..0000000000
--- a/src/mainboard/google/dragonegg/Kconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
- def_bool n
- select BOARD_ROMSIZE_KB_32768
- select DRIVERS_I2C_GENERIC
- select DRIVERS_I2C_HID
- select DRIVERS_SPI_ACPI
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_ESPI
- select HAVE_ACPI_RESUME
- select HAVE_ACPI_TABLES
- select INTEL_LPSS_UART_FOR_CONSOLE
- select MAINBOARD_HAS_CHROMEOS
- select SOC_INTEL_ICELAKE
-
-if BOARD_GOOGLE_BASEBOARD_DRAGONEGG
-
-config CHROMEOS
- bool
- default y
- select GBB_FLAG_FORCE_MANUAL_RECOVERY
-
-config DEVICETREE
- string
- default "variants/baseboard/devicetree.cb"
-
-config DIMM_SPD_SIZE
- int
- default 512
-
-# Select this option to enable use of cr50 SPI TPM on dragon egg.
-config DRAGONEGG_USE_SPI_TPM
- bool
- default y
- select MAINBOARD_HAS_SPI_TPM_CR50
- select MAINBOARD_HAS_TPM2
-
-config DRIVER_TPM_SPI_BUS
- depends on DRAGONEGG_USE_SPI_TPM
- default 0x1
-
-config MAINBOARD_DIR
- string
- default "google/dragonegg"
-
-config MAINBOARD_PART_NUMBER
- string
- default "Dragonegg"
-
-config MAINBOARD_FAMILY
- string
- default "Google_Dragonegg"
-
-config MAX_CPUS
- int
- default 8
-
-config TPM_TIS_ACPI_INTERRUPT
- int
- default 48 # GPE0_DW1_16 (GPP_D16)
-
-config VARIANT_DIR
- string
- default "dragonegg" if BOARD_GOOGLE_DRAGONEGG
-
-config UART_FOR_CONSOLE
- int
- default 0
-
-config VBOOT
- select VBOOT_LID_SWITCH
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select HAS_RECOVERY_MRC_CACHE
- select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-
-endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG
diff --git a/src/mainboard/google/dragonegg/Kconfig.name b/src/mainboard/google/dragonegg/Kconfig.name
deleted file mode 100644
index 8b1bbb1775..0000000000
--- a/src/mainboard/google/dragonegg/Kconfig.name
+++ /dev/null
@@ -1,5 +0,0 @@
-comment "DragonEgg"
-
-config BOARD_GOOGLE_DRAGONEGG
- bool "-> DragonEgg"
- select BOARD_GOOGLE_BASEBOARD_DRAGONEGG
diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc
deleted file mode 100644
index 818df63c84..0000000000
--- a/src/mainboard/google/dragonegg/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += romstage_fsp_params.c
-
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-ramstage-y += mainboard.c
-
-smm-y += smihandler.c
-
-subdirs-y += variants/baseboard
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
-
-subdirs-y += variants/$(VARIANT_DIR)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-
-subdirs-y += spd
diff --git a/src/mainboard/google/dragonegg/board_info.txt b/src/mainboard/google/dragonegg/board_info.txt
deleted file mode 100644
index 3fb6f21d55..0000000000
--- a/src/mainboard/google/dragonegg/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: google
-Board name: Dragon Egg
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/dragonegg/bootblock.c b/src/mainboard/google/dragonegg/bootblock.c
deleted file mode 100644
index 22d63b973c..0000000000
--- a/src/mainboard/google/dragonegg/bootblock.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include <variant/gpio.h>
-
-void bootblock_mainboard_init(void)
-{
- const struct pad_config *pads;
- size_t num;
-
- pads = variant_early_gpio_table(&num);
- gpio_configure_pads(pads, num);
-}
diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c
deleted file mode 100644
index 5a7efefdee..0000000000
--- a/src/mainboard/google/dragonegg/chromeos.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <baseboard/variants.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include <variant/gpio.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
- "EC in RW"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_write_protect_state(void)
-{
- /* Read PCH_WP GPIO. */
- return gpio_get(GPIO_PCH_WP);
-}
-
-void mainboard_chromeos_acpi_generate(void)
-{
- const struct cros_gpio *gpios;
- size_t num;
-
- gpios = variant_cros_gpios(&num);
- chromeos_acpi_gpio_generate(gpios, num);
-}
diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd
deleted file mode 100644
index 7bdeb17ac8..0000000000
--- a/src/mainboard/google/dragonegg/chromeos.fmd
+++ /dev/null
@@ -1,44 +0,0 @@
-FLASH@0xfe000000 0x2000000 {
- SI_ALL@0x0 0x3F0000 {
- SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x36F000
- }
- SI_BIOS@0x1400000 0xC00000 {
- RW_SECTION_A@0x0 0x2d0000 {
- VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x2bffc0
- RW_FWID_A@0x2cffc0 0x40
- }
- RW_SECTION_B@0x2d0000 0x2d0000 {
- VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x2bffc0
- RW_FWID_B@0x2cffc0 0x40
- }
- RW_MISC@0x5a0000 0x30000 {
- UNIFIED_MRC_CACHE@0x0 0x20000 {
- RECOVERY_MRC_CACHE@0x0 0x10000
- RW_MRC_CACHE@0x10000 0x10000
- }
- RW_ELOG(PRESERVE)@0x20000 0x4000
- RW_SHARED@0x24000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
- }
- RW_VPD(PRESERVE)@0x28000 0x2000
- RW_NVRAM(PRESERVE)@0x2a000 0x6000
- }
- RW_LEGACY(CBFS)@0x5d0000 0x230000
- # Make WP_RO region align with SPI vendor
- # memory protected range specification.
- WP_RO@0x800000 0x400000 {
- RO_VPD(PRESERVE)@0x0 0x4000
- RO_SECTION@0x4000 0x3fc000 {
- FMAP@0x0 0x800
- RO_FRID@0x800 0x40
- RO_FRID_PAD@0x840 0x7c0
- GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x30c000
- }
- }
- }
-}
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
deleted file mode 100644
index 15e0498a1e..0000000000
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include "variant/ec.h"
-#include "variant/gpio.h"
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x20110725 // OEM revision
-)
-{
- #include <soc/intel/icelake/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-
- // CPU
- #include <cpu/intel/common/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
- #include <soc/intel/icelake/acpi/southbridge.asl>
- }
- }
-
-#if CONFIG(CHROMEOS)
- // Chrome OS specific
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-#endif
-
- #include <southbridge/intel/common/acpi/sleepstates.asl>
-
- /* Chrome OS Embedded Controller */
- Scope (\_SB.PCI0.LPCB)
- {
- /* ACPI code for EC SuperIO functions */
- #include <ec/google/chromeec/acpi/superio.asl>
- /* ACPI code for EC functions */
- #include <ec/google/chromeec/acpi/ec.asl>
- }
-}
diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c
deleted file mode 100644
index a2fc275219..0000000000
--- a/src/mainboard/google/dragonegg/ec.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <ec/google/chromeec/ec.h>
-#include <variant/ec.h>
-
-void mainboard_ec_init(void)
-{
- const struct google_chromeec_event_info info = {
- .log_events = MAINBOARD_EC_LOG_EVENTS,
- .sci_events = MAINBOARD_EC_SCI_EVENTS,
- .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
- .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
- };
-
- google_chromeec_events_init(&info, acpi_is_wakeup_s3());
-}
diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c
deleted file mode 100644
index 90889ae81d..0000000000
--- a/src/mainboard/google/dragonegg/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <baseboard/variants.h>
-#include <device/device.h>
-#include <ec/ec.h>
-#include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <variant/gpio.h>
-
-static void mainboard_init(void *chip_info)
-{
- size_t num;
- const struct pad_config *gpio_table;
-
- gpio_table = variant_gpio_table(&num);
- gpio_configure_pads(gpio_table, num);
-
- mainboard_ec_init();
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->write_acpi_tables = NULL;
- dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-}
-
-struct chip_operations mainboard_ops = {
- .init = mainboard_init,
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c
deleted file mode 100644
index a70c432e28..0000000000
--- a/src/mainboard/google/dragonegg/romstage_fsp_params.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <assert.h>
-#include <baseboard/variants.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <soc/romstage.h>
-
-static uintptr_t mainboard_get_spd_data(void)
-{
- char *spd_file;
- size_t spd_file_len;
- int spd_index;
- const size_t spd_len = CONFIG_DIMM_SPD_SIZE;
- const char *spd_bin = "spd.bin";
-
- spd_index = variant_memory_sku();
- assert(spd_index >= 0);
- printk(BIOS_INFO, "SPD index %d\n", spd_index);
-
- /* Load SPD data from CBFS */
- spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- /* make sure we have at least one SPD in the file. */
- if (spd_file_len < spd_len)
- die("Missing SPD data.");
-
- /* Make sure we did not overrun the buffer */
- if (spd_file_len < ((spd_index + 1) * spd_len))
- die("Invalid SPD index.");
-
- spd_index *= spd_len;
-
- return (uintptr_t)(spd_file + spd_index);
-}
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
- FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
- struct lpddr4_config mem_params;
-
- memset(&mem_params, 0, sizeof(mem_params));
- variant_memory_params(&mem_params);
-
- if (mem_params.dq_map && mem_params.dq_map_size)
- memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map,
- mem_params.dq_map_size);
-
- if (mem_params.dqs_map && mem_params.dqs_map_size)
- memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map,
- mem_params.dqs_map_size);
-
- memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor,
- mem_params.rcomp_resistor_size);
-
- memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target,
- mem_params.rcomp_target_size);
-
- mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
- mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
- mem_cfg->DqPinsInterleaved = 0;
- mem_cfg->CaVrefConfig = 0x2;
- mem_cfg->ECT = 1; /* Early Command Training Enabled */
- mem_cfg->RefClk = 0; /* Auto Select CLK freq */
- mem_cfg->SpdAddressTable[0] = 0x0;
- mem_cfg->SpdAddressTable[1] = 0x0;
- mem_cfg->SpdAddressTable[2] = 0x0;
- mem_cfg->SpdAddressTable[3] = 0x0;
-}
diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c
deleted file mode 100644
index 59e70018f3..0000000000
--- a/src/mainboard/google/dragonegg/smihandler.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/smm.h>
-#include <ec/google/chromeec/smm.h>
-#include <gpio.h>
-#include <soc/gpio.h>
-#include <intelblocks/smihandler.h>
-#include <variant/ec.h>
-
-void mainboard_smi_espi_handler(void)
-{
- chromeec_smi_process_events();
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
- MAINBOARD_EC_S5_WAKE_EVENTS);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
- MAINBOARD_EC_SMI_EVENTS);
- return 0;
-}
diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex
deleted file mode 100644
index d9014dc1ed..0000000000
--- a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 15 21 91 08 00 40 00 00 02 22 00 00
-00 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex
deleted file mode 100644
index 2f2b18ad08..0000000000
--- a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 15 21 B1 08 00 40 00 00 0A 22 00 00
-48 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc
deleted file mode 100644
index b5dc608707..0000000000
--- a/src/mainboard/google/dragonegg/spd/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-SPD_BIN = $(obj)/spd.bin
-
-SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_2GB # 0b000
-SPD_SOURCES += Hynix_H9HCNNNCPMMLHR_4GB # 0b001
-SPD_SOURCES += Micron_MT53E512M32D2NP_2GB # 0b010
-SPD_SOURCES += Micron_MT53E2G32D8QD_8GB # 0b011
-
-ifeq ($(SPD_SOURCES),)
- SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
-else
- SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-endif
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex
deleted file mode 100644
index 856c05e422..0000000000
--- a/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 15 29 F0 08 00 40 00 00 09 22 00 00
-00 00 05 0F 12 29 05 00 8A 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
deleted file mode 100644
index 71e5456542..0000000000
--- a/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00
-00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc
deleted file mode 100644
index fb7eaf11e9..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc
+++ /dev/null
@@ -1,7 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += gpio.c
-
-romstage-y += memory.c
-
-ramstage-y += gpio.c
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
deleted file mode 100644
index d77633ddd7..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ /dev/null
@@ -1,329 +0,0 @@
-chip soc/intel/icelake
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "PMC_GPP_B"
- register "gpe0_dw1" = "PMC_GPP_D"
- register "gpe0_dw2" = "PMC_GPP_C"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- register "PchHdaDspEnable" = "1"
- register "PchHdaAudioLinkSsp0" = "1"
- register "PchHdaAudioLinkSsp1" = "1"
-
- # FSP configuration
- register "SaGv" = "SaGv_Enabled"
- register "SmbusEnable" = "1"
- register "ScsEmmcHs400Enabled" = "1"
-
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2
- register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)" # Type-C Port 3
- register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
-
- # Enable Pch iSCLK
- register "pch_isclk" = "1"
-
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "1"
- register "PcieRpEnable[6]" = "1"
- register "PcieRpEnable[7]" = "1"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "1"
- register "PcieRpEnable[10]" = "1"
- register "PcieRpEnable[11]" = "1"
- register "PcieRpEnable[12]" = "1"
- register "PcieRpEnable[13]" = "1"
- register "PcieRpEnable[14]" = "1"
- register "PcieRpEnable[15]" = "1"
-
- register "PcieClkSrcUsage[0]" = "0x80"
- register "PcieClkSrcUsage[1]" = "7"
- register "PcieClkSrcUsage[2]" = "8"
- register "PcieClkSrcUsage[3]" = "0x80"
- register "PcieClkSrcUsage[4]" = "0x80"
- register "PcieClkSrcUsage[5]" = "0x80"
- register "PcieClkSrcUsage[6]" = "0x80"
- register "PcieClkSrcUsage[7]" = "0x80"
- register "PcieClkSrcUsage[8]" = "0x80"
- register "PcieClkSrcUsage[9]" = "0x80"
- register "PcieClkSrcUsage[10]" = "0x80"
- register "PcieClkSrcUsage[11]" = "0x80"
- register "PcieClkSrcUsage[12]" = "0x80"
- register "PcieClkSrcUsage[13]" = "0x80"
- register "PcieClkSrcUsage[14]" = "0x80"
- register "PcieClkSrcUsage[15]" = "0x80"
-
- register "PcieClkSrcClkReq[0]" = "0"
- register "PcieClkSrcClkReq[1]" = "1"
- register "PcieClkSrcClkReq[2]" = "2"
- register "PcieClkSrcClkReq[3]" = "3"
- register "PcieClkSrcClkReq[4]" = "4"
- register "PcieClkSrcClkReq[5]" = "5"
- register "PcieClkSrcClkReq[6]" = "6"
- register "PcieClkSrcClkReq[7]" = "7"
- register "PcieClkSrcClkReq[8]" = "8"
- register "PcieClkSrcClkReq[9]" = "9"
- register "PcieClkSrcClkReq[10]" = "10"
- register "PcieClkSrcClkReq[11]" = "11"
- register "PcieClkSrcClkReq[12]" = "12"
- register "PcieClkSrcClkReq[13]" = "13"
- register "PcieClkSrcClkReq[14]" = "14"
- register "PcieClkSrcClkReq[15]" = "15"
-
- register "SerialIoI2cMode" = "{
- [PchSerialIoIndexI2C0] = PchSerialIoPci,
- [PchSerialIoIndexI2C1] = PchSerialIoPci,
- [PchSerialIoIndexI2C2] = PchSerialIoPci,
- [PchSerialIoIndexI2C3] = PchSerialIoPci,
- [PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
- }"
-
- register "SerialIoGSpiMode" = "{
- [PchSerialIoIndexGSPI0] = PchSerialIoPci,
- [PchSerialIoIndexGSPI1] = PchSerialIoPci,
- [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
- }"
-
- register "SerialIoGSpiCsMode" = "{
- [PchSerialIoIndexGSPI0] = 1,
- [PchSerialIoIndexGSPI1] = 1,
- [PchSerialIoIndexGSPI2] = 1,
- }"
-
- register "SerialIoGSpiCsState" = "{
- [PchSerialIoIndexGSPI0] = 0,
- [PchSerialIoIndexGSPI1] = 0,
- [PchSerialIoIndexGSPI2] = 0,
- }"
-
- register "SerialIoUartMode" = "{
- [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
- [PchSerialIoIndexUART1] = PchSerialIoDisabled,
- [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
- }"
-
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
- # GPIO for SD card detect
- register "sdcard_cd_gpio" = "GPP_G5"
-
- # Enable S0ix
- register "s0ix_enable" = "0"
-
- # Intel Common SoC Config
- #+-------------------+---------------------------+
- #| Field | Value |
- #+-------------------+---------------------------+
- #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
- #| GSPI0 | cr50 TPM. Early init is |
- #| | required to set up a BAR |
- #| | for TPM communication |
- #| | before memory is up |
- #| pch_thermal_trip | PCH Trip Temperature |
- #+-------------------+---------------------------+
-
- register "common_soc_config" = "{
- .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- .gspi[0] = {
- .speed_mhz = 1,
- .early_init = 1,
- },
- .i2c[3] = {
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 176,
- .scl_hcnt = 95,
- .sda_hold = 36,
- }
- },
- .pch_thermal_trip = 77,
- }"
-
- # GPIO PM programming
- register "gpio_override_pm" = "1"
-
- # GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
-
- device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 off end # SA Thermal device
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 14.0 on
- chip drivers/usb/acpi
- register "desc" = ""Root Hub""
- register "type" = "UPC_TYPE_HUB"
- device usb 0.0 on
- chip drivers/usb/acpi
- register "desc" = ""USB2 Type-C Right""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- device usb 2.0 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Rear Left""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- device usb 2.1 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Front Left""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- device usb 2.2 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Right""
- register "type" = "UPC_TYPE_USB3_A"
- device usb 2.3 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Bluetooth""
- register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.4 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Camera""
- register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.5 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Right""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- device usb 3.0 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Rear Left""
- register "type" = "UPC_TYPE_USB3_A"
- device usb 3.1 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Front Right""
- register "type" = "UPC_TYPE_USB3_A"
- device usb 3.2 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Right""
- register "type" = "UPC_TYPE_USB3_A"
- device usb 3.3 on end
- end
- end
- end
- end # USB xHCI
- device pci 14.2 off end # PMC SRAM
- device pci 14.1 off end # USB xDCI (OTG)
- chip drivers/intel/wifi
- register "wake" = "GPE0_PME_B0"
- device pci 14.3 on end # CNVi wifi
- end
- device pci 14.5 on end # SDCard
- device pci 15.0 on end # I2C #0
- device pci 15.1 on
- chip drivers/i2c/generic
- register "hid" = ""ELAN0000""
- register "desc" = ""ELAN Touchpad""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)"
- register "wake" = "GPE0_DW1_00"
- device i2c 15 on end
- end
- end # I2C #1
- device pci 15.2 on end # I2C #2
- device pci 15.3 on
- chip drivers/i2c/max98373
- register "vmon_slot_no" = "4"
- register "imon_slot_no" = "5"
- register "uid" = "0"
- register "desc" = ""RIGHT SPEAKER AMP""
- register "name" = ""MAXR""
- device i2c 31 on end
- end
- chip drivers/i2c/max98373
- register "vmon_slot_no" = "6"
- register "imon_slot_no" = "7"
- register "uid" = "1"
- register "desc" = ""LEFT SPEAKER AMP""
- register "name" = ""MAXL""
- device i2c 32 on end
- end
- end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 off end # SATA
- device pci 19.0 on end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 on end # UART #2
- device pci 1a.0 on end # eMMC
- device pci 1c.0 on
- chip drivers/intel/wifi
- register "wake" = "GPE0_DW0_06"
- device pci 00.0 on end
- end
- end # PCI Express Port 1 x4 SLOT1
- device pci 1c.4 off end # PCI Express Port 5 x1 SLOT2/LAN
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 on
- chip drivers/spi/acpi
- register "hid" = "ACPI_DT_NAMESPACE_HID"
- register "compat_string" = ""google,cr50""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
- device spi 0 on end
- end
- end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
- end
-end
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
deleted file mode 100644
index b0efd00698..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <commonlib/helpers.h>
-
-/* Pad configuration in ramstage*/
-static const struct pad_config gpio_table[] = {
-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
-/* I2S2_RXD */ PAD_CFG_GPI(GPP_A10, NONE, PLTRST),
-/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ PAD_CFG_GPO(GPP_A14, 0, DEEP),
-/* USB_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-/* WLAN_PCIE_WAKE_L */ PAD_CFG_GPI_SCI(GPP_B6, NONE, DEEP, EDGE_SINGLE,
- INVERT),
-/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),
-/* PCH_SPI_FPMCU_F7_CS_L */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
-/* PEN_INT_ODL */ PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
-/* GPP_C5_STRAP */ PAD_CFG_GPO(GPP_C5, 1, DEEP),
-/* TCH_INT_ODL */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST),
-/* TCH_RST_ODL */ PAD_CFG_GPO(GPP_C11, 0, PLTRST),
-/* M2_SHUTDOWN+L */ PAD_CFG_GPO(GPP_C12, 1, PLTRST),
-/* M2_RESET_L */ PAD_CFG_GPO(GPP_C13, 1, PLTRST),
-/* M2_INT_L */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST),
-/* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST),
-/* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST),
-/* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST),
-/* TRACKPAD_WAKE */ PAD_CFG_GPI_SCI(GPP_D0, NONE, DEEP, EDGE_SINGLE,
- INVERT),
-/* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D1, NONE, DEEP, EDGE_SINGLE,
- INVERT),
-/* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1),
-/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,
- INVERT),
-/* GPP_E6_STRAP */ PAD_CFG_GPO(GPP_E6, 1, DEEP),
-/* USB_C0_SBU_1_DC */ PAD_CFG_GPO(GPP_E22, 1, PLTRST),
-/* USB_C0_SBU_2_DC */ PAD_CFG_GPO(GPP_E23, 0, DEEP),
-/* CNV_RF_RESET_N */ PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1),
-/* CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2),
-/* SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_F6, NONE, DEEP, LEVEL, NONE),
-/* SPKR_RST_L */ PAD_CFG_GPO(GPP_F19, 1, DEEP),
-/* SD_CD# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP),
-/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
-/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
-/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST),
-/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST),
-/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST),
-/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST),
-/* I2S0_SCLK */ PAD_CFG_GPO(GPP_R0, 1, DEEP),
-/* I2S0_SFRM */ PAD_CFG_GPO(GPP_R1, 1, DEEP),
-/* I2S0_TXD */ PAD_CFG_GPO(GPP_R2, 1, DEEP),
-/* I2S0_RXD */ PAD_CFG_GPI(GPP_R3, NONE, DEEP),
-};
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP),
-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
-/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL,
- INVERT),
-};
-
-const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
-{
- *num = ARRAY_SIZE(gpio_table);
- return gpio_table;
-}
-
-const struct pad_config *__attribute__((weak))
- variant_early_gpio_table(size_t *num)
-{
- *num = ARRAY_SIZE(early_gpio_table);
- return early_gpio_table;
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(39, CROS_GPIO_DEVICE_NAME),
-};
-
-const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
-{
- *num = ARRAY_SIZE(cros_gpios);
- return cros_gpios;
-}
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h
deleted file mode 100644
index 6471385660..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_EC_H__
-#define __BASEBOARD_EC_H__
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#include <variant/gpio.h>
-
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/*
- * EC can wake from S3 with lid or power button or key press or
- * mode change event.
- */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-/*
- * ACPI related definitions for ASL code.
- */
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
-#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
-
-#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
-#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
-#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
-
-#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h
deleted file mode 100644
index fc7e94a114..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_GPIO_H__
-#define __BASEBOARD_GPIO_H__
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* EC in RW */
-#define GPIO_EC_IN_RW GPP_B8
-
-/* BIOS Flash Write Protect */
-#define GPIO_PCH_WP GPP_B7
-
-/* eSPI virtual wire reporting */
-#define EC_SCI_GPI GPE0_ESPI
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE GPE0_LAN_WAK
-
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0 GPP_H12
-#define GPIO_MEM_CONFIG_1 GPP_H13
-#define GPIO_MEM_CONFIG_2 GPP_H14
-#define GPIO_MEM_CONFIG_3 GPP_H15
-
-#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h
deleted file mode 100644
index 83f9d9583f..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_VARIANTS_H__
-#define __BASEBOARD_VARIANTS_H__
-
-#include <soc/gpio.h>
-#include <stdint.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/*
- * The next set of functions return the gpio table and fill in the number of
- * entries for each table.
- */
-const struct pad_config *variant_gpio_table(size_t *num);
-const struct pad_config *variant_early_gpio_table(size_t *num);
-const struct cros_gpio *variant_cros_gpios(size_t *num);
-
-struct lpddr4_config {
- const void *dq_map;
- size_t dq_map_size;
- const void *dqs_map;
- size_t dqs_map_size;
- const void *rcomp_resistor;
- size_t rcomp_resistor_size;
- const void *rcomp_target;
- size_t rcomp_target_size;
-};
-void variant_memory_params(struct lpddr4_config *mem_config);
-int variant_memory_sku(void);
-#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c
deleted file mode 100644
index adb9ba63fe..0000000000
--- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/cpu.h>
-#include <baseboard/variants.h>
-#include <gpio.h>
-#include <intelblocks/mp_init.h>
-#include <variant/gpio.h>
-
-/* DQ byte map */
-static const u8 dq_map[][12] = {
- { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
-};
-
-/* DQS CPU<>DRAM map */
-static const u8 dqs_map[][8] = {
- { 0, 1, 2, 3, 4, 5, 6, 7 },
- { 0, 1, 2, 3, 5, 4, 7, 6 },
-};
-
-/* Rcomp resistor */
-static const u16 rcomp_resistor[] = { 100, 100, 100 };
-
-void __weak variant_memory_params(struct lpddr4_config *mem_config)
-{
- /* Rcomp target */
- static const u16 rcomp_target_es0[] = { 80, 40, 40, 40, 30 };
- static const u16 rcomp_target_es1[] = { 60, 20, 20, 20, 20 };
-
- mem_config->dq_map = dq_map;
- mem_config->dq_map_size = sizeof(dq_map);
- mem_config->dqs_map = dqs_map;
- mem_config->dqs_map_size = sizeof(dqs_map);
- mem_config->rcomp_resistor = rcomp_resistor;
- mem_config->rcomp_resistor_size = sizeof(rcomp_resistor);
- if (cpu_get_cpuid() == CPUID_ICELAKE_A0) {
- mem_config->rcomp_target = rcomp_target_es0;
- mem_config->rcomp_target_size = sizeof(rcomp_target_es0);
- } else {
- mem_config->rcomp_target = rcomp_target_es1;
- mem_config->rcomp_target_size = sizeof(rcomp_target_es1);
- }
-}
-
-int __weak variant_memory_sku(void)
-{
- gpio_t spd_gpios[] = {
- GPIO_MEM_CONFIG_0,
- GPIO_MEM_CONFIG_1,
- GPIO_MEM_CONFIG_2,
- GPIO_MEM_CONFIG_3,
- };
-
- return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
-}
diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h
deleted file mode 100644
index 61288a4009..0000000000
--- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __MAINBOARD_EC_H__
-#define __MAINBOARD_EC_H__
-
-#include <baseboard/ec.h>
-
-#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h
deleted file mode 100644
index 33ccb11351..0000000000
--- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __MAINBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
-
-#include <baseboard/gpio.h>
-
-#endif /* __MAINBOARD_GPIO_H__ */