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authorEd Swierk <eswierk@arastra.com>2008-04-01 02:48:12 +0000
committerEd Swierk <eswierk@arastra.com>2008-04-01 02:48:12 +0000
commit06ae6395964b2eb84be10533a7e14049778a45a9 (patch)
treeea255e523d668bad224d14c4f5420cfb0861cc8c /src
parent868de9838c8ea97b8d27a0bc97828f1964536084 (diff)
downloadcoreboot-06ae6395964b2eb84be10533a7e14049778a45a9.tar.xz
Tiny style fix for consistency (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/i3100/i3100_early_lpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c
index 742cffa2ca..7afe8c1ac2 100644
--- a/src/southbridge/intel/i3100/i3100_early_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_early_lpc.c
@@ -28,7 +28,7 @@ static void i3100_enable_superio(void)
static void i3100_halt_tco_timer(void)
{
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Temporarily enable the ACPI I/O range at 0x4000 */
pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));