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authorSubrata Banik <subrata.banik@intel.com>2017-07-12 15:31:06 +0530
committerMartin Roth <martinroth@google.com>2017-07-17 15:16:37 +0000
commit0755ab98a5f0d6632a4fc856d8812f5e70983a13 (patch)
treec379cf972fcd13bdf7f04a26063ce97b2bb85de3 /src
parent0beac81f64162fe8374c9f008b9ea811f5064b34 (diff)
downloadcoreboot-0755ab98a5f0d6632a4fc856d8812f5e70983a13.tar.xz
intel/fsp: Add and use new post codes for FSP phase indication
New post codes are POST_FSP_MEMORY_EXIT POST_FSP_SILICON_EXIT This patch will make it more consistent to debug FSP hang and reset issues. Bug=none Branch=none TEST=Build and Boot on eve Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c2
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c2
-rw-r--r--src/include/console/post_codes.h14
3 files changed, 16 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 43888c1bad..b08ee1e768 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -361,7 +361,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
- post_code(POST_FSP_MEMORY_INIT);
+ post_code(POST_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
fsp_debug_after_memory_init(status);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9f0bf7c892..bda88d11ca 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -49,7 +49,7 @@ static void do_silicon_init(struct fsp_header *hdr)
post_code(POST_FSP_SILICON_INIT);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POST_FSP_SILICON_EXIT);
fsp_debug_after_silicon_init(status);
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 1368aa865c..0277337a0a 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -273,6 +273,20 @@
#define POST_OS_ENTER_WAKE 0x97
/**
+ * \brief After calling FSP MemoryInit
+ *
+ * FSP binary returned from MemoryInit phase
+ */
+#define POST_FSP_MEMORY_EXIT 0x98
+
+/**
+ * \brief After calling FSP SiliconInit
+ *
+ * FSP binary returned from SiliconInit phase
+ */
+#define POST_FSP_SILICON_EXIT 0x99
+
+/**
* \brief Entry into elf boot
*
* This POST code is called right before invoking jmp_to_elf_entry()