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authorLijian Zhao <lijian.zhao@intel.com>2017-10-04 14:32:06 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-18 19:46:33 +0000
commit0b21ad9e8012dba2f4365bfbc3b51e6637eec588 (patch)
tree351212996bf76242988a270c53f671fdaa980cf4 /src
parent580bc412c7449a3592e80ac737c3492af6594dfa (diff)
downloadcoreboot-0b21ad9e8012dba2f4365bfbc3b51e6637eec588.tar.xz
intel/cannonlake_rvp: Declare PCIE clock usage
Define PCI express clock usage for cannonlake u and cannonlake y rvp based on board design. TEST=Bootable into OS. Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb31
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb29
2 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 54d2a69a0f..627e7d25a6 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -33,6 +33,37 @@ chip soc/intel/cannonlake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[1]" = "1"
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpEnable[11]" = "1"
+ register "PcieRpEnable[12]" = "1"
+ register "PcieRpEnable[13]" = "1"
+ register "PcieRpEnable[14]" = "1"
+ register "PcieRpEnable[15]" = "1"
+
+ register "PcieClkSrcUsage[0]" = "1"
+ register "PcieClkSrcUsage[1]" = "8"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+ register "PcieClkSrcUsage[3]" = "13"
+ register "PcieClkSrcUsage[4]" = "4"
+ register "PcieClkSrcUsage[5]" = "14"
+
+ register "PcieClkSrcClkReq[0]" = "0"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcClkReq[5]" = "5"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index bb75605b11..d417e9057e 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -33,6 +33,35 @@ chip soc/intel/cannonlake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[1]" = "1"
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpEnable[11]" = "1"
+ register "PcieRpEnable[12]" = "1"
+ register "PcieRpEnable[13]" = "1"
+
+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[1]" = "8"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+ register "PcieClkSrcUsage[3]" = "14"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[5]" = "1"
+
+ register "PcieClkSrcClkReq[0]" = "0"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcClkReq[5]" = "5"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device