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authorKatherine Hsieh <Katherine.Hsieh@quantatw.com>2018-04-13 06:24:51 +0000
committerAaron Durbin <adurbin@chromium.org>2018-04-16 02:39:34 +0000
commit0c557cd983e021b1675fb1688784652d4815f0ba (patch)
tree409ec7c22d114f97649d981de37c3e65359d73f0 /src
parentfa529bb940a413d95322e22b29c29531f4721d52 (diff)
downloadcoreboot-0c557cd983e021b1675fb1688784652d4815f0ba.tar.xz
Revert "mb/google/reef/sand: Override USB2 phy settings"
This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/reef/variants/sand/devicetree.cb16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index e53af885e0..16889bb8c9 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -112,22 +112,6 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
- # Override USB2 PER PORT register (PORT 1)
- register "usb2eye[1]" = "{
- .Usb20PerPortPeTxiSet = 4,
- .Usb20PerPortTxiSet = 4,
- .Usb20IUsbTxEmphasisEn = 1,
- .Usb20PerPortTxPeHalf = 0,
- }"
-
- # Override USB2 PER PORT register (PORT 4)
- register "usb2eye[4]" = "{
- .Usb20PerPortPeTxiSet = 7,
- .Usb20PerPortTxiSet = 7,
- .Usb20IUsbTxEmphasisEn = 1,
- .Usb20PerPortTxPeHalf = 0,
- }"
-
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF