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| author | Shelley Chen <shchen@google.com> | 2020-05-20 09:54:26 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:06:38 +0000 |
| commit | 1408798637125f1707ded7215e22461c623a79a8 (patch) | |
| tree | 8d03b40aa30f1f8d1653b149b9fac5f239f14f3d /src | |
| parent | d9cd064ac66148293385671160e56bd1c2664015 (diff) | |
| download | coreboot-1408798637125f1707ded7215e22461c623a79a8.tar.xz | |
Mushu: Enable PCIe 1d.4 to enable dgpu
BUG=b:147249494,b:147249494
BRANCH=None
TEST=boot up mushu
check cbmem -1 to make sure PCIe 1d.4 is enabled
Change-Id: I36404217f0ecffb0cce1105e76f507c9062df053
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/mushu/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index db86d68204..100f7d5603 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -185,6 +185,7 @@ chip soc/intel/cannonlake device i2c 1a on end end end #I2C #4 + device pci 1d.4 on end # PCI Express port 13 device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" |