diff options
| author | Mathew King <mathewk@chromium.org> | 2021-03-19 11:39:14 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-24 19:47:08 +0000 |
| commit | 156be2db5ac09f9daa5c7843bfecfad4902e99a8 (patch) | |
| tree | 1513882bcdc94ee34c841ff93011a3e3851ba36e /src | |
| parent | 39ef89033624a2d14b0c77cdbdf287dd7d7059e1 (diff) | |
| download | coreboot-156be2db5ac09f9daa5c7843bfecfad4902e99a8.tar.xz | |
mb/google/guybrush: Temporary fix to set eSPI mux
This change allows guybrush EC communication while other patches
in the SOC code are worked on.
BUG=b:183149183
TEST=Boot guybrush with EC comunication
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 4b11bd0545..92de72fee4 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -1,14 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> #include <delay.h> #include <gpio.h> #include <soc/gpio.h> +#include <soc/pci_devs.h> void bootblock_mainboard_early_init(void) { size_t num_gpios; + uint32_t dword; const struct soc_amd_gpio *gpios; if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { @@ -16,6 +21,23 @@ void bootblock_mainboard_early_init(void) program_gpios(gpios, num_gpios); } + printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); + + dword = pci_read_config32(SOC_LPC_DEV, 0x78); + dword &= 0xFFFFF9F3; + dword |= 0x200; + pci_write_config32(SOC_LPC_DEV, 0x78, dword); + pci_write_config32(SOC_LPC_DEV, 0x44, 0); + pci_write_config32(SOC_LPC_DEV, 0x48, 0); + + dword = pm_read32(0x90); + dword |= 1 << 16; + pm_write32(0x90, dword); + + dword = pm_read32(0x74); + dword |= 3 << 10; + pm_write32(0x74, dword); + if (CONFIG(GPIO_SIGN_OF_LIFE)) { for (int x = 0; x < 20; x++) { gpio_set(GPIO_31, 1); |