{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()

This patch removes all local definitions of sub_system functions and make
use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus
devices as well.

Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

10 files changed, 11 insertions, 109 deletions

diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index 16bc314b90..344cd8027e 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -65,20 +65,8 @@ static const char *pcie_acpi_name(const struct device *dev)
 }
 #endif
 
-static void
-pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)
-{
-	/* NOTE: This is not the default position! */
-	if (!ven || !device)
-		pci_write_config32(dev, 0x94,
-				   pci_read_config32(dev, 0));
-	else
-		pci_write_config32(dev, 0x94,
-				   ((device & 0xffff) << 16) | (ven & 0xffff));
-}
-
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 32135eedbb..472e8da465 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -649,16 +649,6 @@ static void pch_pcie_enable(struct device *dev)
 		root_port_commit_config();
 }
 
-static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
-	unsigned int device)
-{
-	/* NOTE: This is not the default position! */
-	if (!vendor || !device)
-		pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
-	else
-		pci_write_config32(dev, 0x94, (device << 16) | vendor);
-}
-
 static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
 {
 	/* Set max snoop and non-snoop latency for Broadwell */
@@ -666,7 +656,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
 }
 
 static struct pci_operations pcie_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
 };
 
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 82957657f5..d74b09826c 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -25,8 +25,6 @@
 #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE	0x1003
 /* Latency tolerance reporting, max snoop latency value 3.14ms */
 #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE	0x1003
-/* PCI-E Sub-System ID */
-#define PCIE_SUBSYSTEM_VENDOR_ID	0x94
 
 static void pch_pcie_init(struct device *dev)
 {
@@ -72,16 +70,9 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
 			PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
 }
 
-static void pcie_dev_set_subsystem(struct device *dev,
-		unsigned int vendor, unsigned int device)
-{
-	pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
-			((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
 static struct pci_operations pcie_ops = {
 	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
-	.set_subsystem = pcie_dev_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 39c53e88fc..0bc75b54a5 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -306,21 +306,8 @@ static const char *pch_pcie_acpi_name(const struct device *dev)
 	return NULL;
 }
 
-static void pcie_set_subsystem(struct device *dev, unsigned vendor,
-			       unsigned device)
-{
-	/* NOTE: This is not the default position! */
-	if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
-	} else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
-	}
-}
-
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 9446527c7b..3e5dbc3e87 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -252,22 +252,8 @@ static void ich_pcie_enable(struct device *dev)
 		root_port_commit_config(dev);
 }
 
-
-static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
-			       unsigned int device)
-{
-	/* NOTE: This is not the default position! */
-	if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
-	} else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
-	}
-}
-
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index a36fdc617c..3b90ce6471 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -95,19 +95,6 @@ static void pci_init(struct device *dev)
 	}
 }
 
-static void pcie_set_subsystem(struct device *dev, unsigned vendor,
-			       unsigned device)
-{
-	/* NOTE: 0x94 is not the default position! */
-	if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
-	} else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
-	}
-}
-
 static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
@@ -121,7 +108,7 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 }
 
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index fb90cd962a..84b2b6a3fa 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -95,19 +95,6 @@ static void pci_init(struct device *dev)
 	}
 }
 
-static void pcie_set_subsystem(struct device *dev, unsigned vendor,
-			       unsigned device)
-{
-	/* NOTE: 0x94 is not the default position! */
-	if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
-	} else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
-	}
-}
-
 static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_i82801jx_config *config = dev->chip_info;
@@ -121,7 +108,7 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 }
 
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 695abf2605..2a8b44e0fc 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -727,21 +727,8 @@ static void pch_pcie_enable(struct device *dev)
 		root_port_commit_config();
 }
 
-static void pcie_set_subsystem(struct device *dev, unsigned vendor,
-			       unsigned device)
-{
-	/* NOTE: This is not the default position! */
-	if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
-	} else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
-	}
-}
-
 static struct pci_operations pci_ops = {
-	.set_subsystem = pcie_set_subsystem,
+	.set_subsystem = pci_dev_set_subsystem,
 };
 
 static struct device_operations device_ops = {
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 4d8b6e6322..c94722cb52 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -200,8 +200,8 @@ static void rl5c476_set_subsystem(struct device *dev, unsigned vendor,
 	/* Enable subsystem id register writes */
 	pci_write_config16(dev, 0x82, miscreg | 0x40);
 
-	pci_write_config16(dev, 0x40, vendor);
-	pci_write_config16(dev, 0x42, device);
+	pci_dev_set_subsystem(dev, vendor, device);
+
 	/* restore original contents */
 	pci_write_config16(dev, 0x82, miscreg);
 }
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
index f84d86680f..bfb5ab92df 100644
--- a/src/southbridge/ti/pci1x2x/pci1x2x.c
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -46,8 +46,7 @@ static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor,
 	 * to the sub-vendor/device ids at 40 and 42.
 	 */
 	pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
-	pci_write_config16(dev, 0x40, vendor);
-	pci_write_config16(dev, 0x42, device);
+	pci_dev_set_subsystem(dev, vendor, device);
 	pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
 }