diff options
| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-11-12 02:33:31 +0000 |
|---|---|---|
| committer | Corey Osgood <corey.osgood@gmail.com> | 2007-11-12 02:33:31 +0000 |
| commit | 18517e8a1fc9fdbf56a01a0122ec5e31e48fa2aa (patch) | |
| tree | 5252da8ccf5333f42bb08604141b63a31b4f7c05 /src | |
| parent | c716254e16fc1c7fe7bbf35e9110dd3b4495880e (diff) | |
| download | coreboot-18517e8a1fc9fdbf56a01a0122ec5e31e48fa2aa.tar.xz | |
Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO
configuration.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/Config.lb | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index 4b19454949..8d6ab1ba61 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -239,7 +239,12 @@ chip northbridge/amd/amdk8/root_complex device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + # Floppy and any LDN + device pnp 2e.0 off + # Watchdog from CLKIN, CLKIN = 24 MHz + irq 0x23 = 0x11 + # Serial Flash (SPI only) + #0x24 = 0x1a io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +274,52 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + # pin 84 is not GP10 + irq 0x25 = 0x0 + # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # pin 13 is GP35 + irq 0x27 = 0x20 + # pin 70 is not GP46 + #0x28 = 0x0 + # pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + #0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + #io 0x64 = 0x820 + # watch dog force timeout (parallel flash only) + #0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + #0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + #0xc3 = 0x0 + # SIO pin set 1 input mode + #0xc8 = 0x0 + # SIO pin set 2 mixed input/output mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + #0xcb = 0x0 + # Generate SMI# on EC IRQ + #0xf0 = 0x10 + # SMI# level trigger + #0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +356,7 @@ chip northbridge/amd/amdk8/root_complex device i2c 57 on end end end # SM +#WTF?!? We already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1 |