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authorDavid Hendricks <dhendrix@chromium.org>2013-03-29 15:40:34 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-30 03:33:40 +0100
commit1877ceed212b586f13277b4b2057598d39b78894 (patch)
tree699efc76f60a3f4b2fd810887339c84a22a1dadb /src
parent58779358362ef0c9ed433c310416a93c8b9c9211 (diff)
downloadcoreboot-1877ceed212b586f13277b4b2057598d39b78894.tar.xz
armv7: change some unsigned ints to uint32_t
Use register-sized types in case the inline assembler doesn't do so automatically. Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2983 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/arch/armv7/include/arch/cache.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 3e0ff2e1ce..1db86dc57c 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -220,9 +220,9 @@ static inline void write_csselr(uint32_t val)
}
/* read L2 control register (L2CTLR) */
-static inline unsigned int read_l2ctlr(void)
+static inline uint32_t read_l2ctlr(void)
{
- unsigned int val = 0;
+ uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
return val;
}
@@ -239,9 +239,9 @@ static inline void write_l2ctlr(uint32_t val)
}
/* read system control register (SCTLR) */
-static inline unsigned int read_sctlr(void)
+static inline uint32_t read_sctlr(void)
{
- unsigned int val;
+ uint32_t val;
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
return val;
}