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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-01-18 19:50:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-19 09:03:42 +0000 |
| commit | 193aac88353574e5ab9de5fd50d240ae8249c155 (patch) | |
| tree | 32484099028b67da6ef34411be1f0c0310fc6aa4 /src | |
| parent | fc63f8d5a955c02c7621ba981b7e5594166f6c21 (diff) | |
| download | coreboot-193aac88353574e5ab9de5fd50d240ae8249c155.tar.xz | |
cpu/x86/sipi_vector.S: Fix reading MCU revision
Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content
is required. This is how things are done in
cpu/intel/microcode/microcode.c.
The "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
also recommends this: "It is recommended that this field be preloaded
with 0 prior to executing CPUID" (this field being %edx).
Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/x86/sipi_vector.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index e1b90890ed..f9b29576bd 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -115,6 +115,10 @@ _start: jz microcode_done /* Bypass if no microde exists. */ /* Get the Microcode version. */ + xorl %eax, %eax + xorl %edx, %edx + movl $IA32_BIOS_SIGN_ID, %ecx + wrmsr mov $1, %eax cpuid mov $IA32_BIOS_SIGN_ID, %ecx |