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authorTristan Corrick <tristan@corrick.kiwi>2018-08-01 02:55:09 +1200
committerFelix Held <felix-coreboot@felixheld.de>2018-08-03 11:18:03 +0000
commit19961a4b1b5e8d78855c80740528042e47cf899f (patch)
tree54af0669bff316b7f19f9909d200a08371c009ff /src
parentad691ad65d08f3e54f003fd8794266cf2e0fd1e9 (diff)
downloadcoreboot-19961a4b1b5e8d78855c80740528042e47cf899f.tar.xz
superio/nuvoton/nct6776/acpi: Add parallel port support
Exposing the parallel port via ACPI causes Linux to automatically detect the parallel port and load the appropriate modules. Tested on an ASUS P8H61-M LX with Linux 4.9.110 and 4.17.8. However, no parallel port device has been tested. Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/superio/nuvoton/nct6776/acpi/superio.asl30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl
index b985115111..980eab9cf8 100644
--- a/src/superio/nuvoton/nct6776/acpi/superio.asl
+++ b/src/superio/nuvoton/nct6776/acpi/superio.asl
@@ -23,6 +23,7 @@
* devices, disabling and reenabling logical devices.
*
* LDN State
+ * 0x1 PP Implemented, untested
* 0x2 SP1 Implemented, untested
* 0x5 KBC Implemented, untested
* 0x8 GPIO Implemented, untested
@@ -31,6 +32,7 @@
* Controllable through preprocessor defines:
* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
+ * NCT6776_SHOW_PP If defined, the parallel port will be exposed.
* NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed.
* NCT6776_SHOW_KBC If defined, the Keyboard Controller will be exposed.
* NCT6776_SHOW_GPIO If defined, GPIO support will be exposed.
@@ -85,6 +87,8 @@ Device(SUPERIO_DEV) {
PNP_IRQ0, 8, /* First IRQ */
Offset (0x72),
PNP_IRQ1, 8, /* Second IRQ */
+ Offset (0x74),
+ PNP_DMA0, 8, /* DRQ */
}
Method (_CRS)
@@ -107,6 +111,32 @@ Device(SUPERIO_DEV) {
#define PNP_EXIT_MAGIC_1ST 0xaa
#include <superio/acpi/pnp_config.asl>
+#ifdef NCT6776_SHOW_PP
+ #undef SUPERIO_PNP_HID
+ #undef SUPERIO_PNP_LDN
+ #undef SUPERIO_PNP_DDN
+ #undef SUPERIO_PNP_PM_REG
+ #undef SUPERIO_PNP_PM_VAL
+ #undef SUPERIO_PNP_PM_LDN
+ #undef SUPERIO_PNP_IO0
+ #undef SUPERIO_PNP_IO1
+ #undef SUPERIO_PNP_IO2
+ #undef SUPERIO_PNP_IRQ0
+ #undef SUPERIO_PNP_IRQ1
+ #undef SUPERIO_PNP_DMA
+ /*
+ * The extra code required to dynamically reflect ECP in the HID
+ * isn't currently justified, so the HID is hardcoded as not
+ * using ECP. "PNP0401" would indicate ECP.
+ */
+ #define SUPERIO_PNP_HID "PNP0400"
+ #define SUPERIO_PNP_LDN 1
+ #define SUPERIO_PNP_IO0 0x08, 0x08
+ #define SUPERIO_PNP_IRQ0
+ #define SUPERIO_PNP_DMA
+ #include <superio/acpi/pnp_generic.asl>
+#endif
+
#ifdef NCT6776_SHOW_SP1
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN