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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-05 16:29:41 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-07 15:52:01 +0000
commit1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9 (patch)
tree1751b8ebc3e6b6657d41d1b92e3e070fa8c8bb3e /src
parentba092a9ab6e87fec458d6557d0114147e2713686 (diff)
downloadcoreboot-1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9.tar.xz
{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
Use already defined system_reset() and full_reset() functions. Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/gm45/early_reset.c8
-rw-r--r--src/northbridge/intel/pineview/raminit.c7
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c7
-rw-r--r--src/northbridge/intel/x4x/raminit.c5
4 files changed, 10 insertions, 17 deletions
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 9f919cfbcd..3f095a256f 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -16,8 +16,9 @@
#include <types.h>
#include <arch/io.h>
+#include <cf9_reset.h>
#include <device/pci_ops.h>
-#include <halt.h>
+
#include "gm45.h"
void gm45_early_reset(void/*const timings_t *const timings*/)
@@ -63,8 +64,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
/* Normally, we would set this after successful raminit. */
MCHBAR32(DCC_MCHBAR) |= (1 << 19);
- /* Perform system reset through CF9 interface. */
- outb(0x02, 0xcf9); /* Set system reset bit. */
- outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
- halt();
+ system_reset();
}
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 48bca36faa..144905fb92 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <cf9_reset.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
@@ -1744,10 +1745,8 @@ static void sdram_checkreset(void)
}
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3);
- if (reset) {
- printk(BIOS_DEBUG, "Power cycle reset...\n");
- outb(0xe, 0xcf9);
- }
+ if (reset)
+ full_reset();
}
static void sdram_dradrb(struct sysinfo *s)
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3fab3be85d..43316a2f22 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <console/console.h>
#include <arch/io.h>
+#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <timestamp.h>
@@ -47,10 +48,8 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- halt ();
- }
+ if (MCHBAR16(SSKPD) == 0xCAFE)
+ system_reset();
if (bist == 0)
enable_lapic();
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 4d5bdce9ac..60d3b55531 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -22,7 +22,6 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <arch/cpu.h>
-#include <halt.h>
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
#else
@@ -624,9 +623,7 @@ static void checkreset_ddr2(int boot_path)
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
- printk(BIOS_DEBUG, "Reset...\n");
- outb(0xe, 0xcf9);
- asm ("hlt");
+ full_reset();
}
pmcon2 |= 0x80;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);