soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters

Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.

BUG=b:161923068

Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 13 insertions, 7 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index e355b5b14a..4a01a12cc0 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -51,6 +51,8 @@ chip soc/amd/picasso
 
 	register "xhci0_force_gen1" = "0"
 
+	register "has_usb2_phy_tune_params" = "1"
+
 	# Controller0 Port0 Default
 	register "usb_2_port_0_tune_params" = "{
 		.com_pds_tune = 0x03,
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 283e7a07a4..986c444e14 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -51,6 +51,8 @@ chip soc/amd/picasso
 
 	register "xhci0_force_gen1" = "0"
 
+	register "has_usb2_phy_tune_params" = "1"
+
 	# Controller0 Port0 Default
 	register "usb_2_port_0_tune_params" = "{
 		.com_pds_tune = 0x03,
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 3bcd3cc5c4..d3c9a0721b 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -133,13 +133,13 @@ struct soc_amd_picasso_config {
 
 	uint8_t xhci0_force_gen1;
 
+	uint8_t has_usb2_phy_tune_params;
 	struct usb2_phy_tune usb_2_port_0_tune_params;
 	struct usb2_phy_tune usb_2_port_1_tune_params;
 	struct usb2_phy_tune usb_2_port_2_tune_params;
 	struct usb2_phy_tune usb_2_port_3_tune_params;
 	struct usb2_phy_tune usb_2_port_4_tune_params;
 	struct usb2_phy_tune usb_2_port_5_tune_params;
-
 };
 
 typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index d07c38493a..d280bffc47 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -102,12 +102,14 @@ static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
 
 	scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
 
-	memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num);
-	memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num);
-	memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num);
-	memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num);
-	memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num);
-	memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num);
+	if (cfg->has_usb2_phy_tune_params) {
+		memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num);
+		memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num);
+		memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num);
+		memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num);
+		memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num);
+		memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num);
+	}
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)