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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:24:21 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:24:21 +0000 |
| commit | 1f93fea160fff042f7d5467c56eaf2fc0286995f (patch) | |
| tree | 19b70c9576ea9869caed82def385177d4a08488e /src | |
| parent | 0e5d3e16b494aafa3c08a28a0484ee0845d84512 (diff) | |
| download | coreboot-1f93fea160fff042f7d5467c56eaf2fc0286995f.tar.xz | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
BKDG says nbSynPtrAdj may also be 6 sometimes.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 20 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 6 |
2 files changed, 22 insertions, 4 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index fc54d16e23..37ae426c2e 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -321,14 +321,26 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xA0, dword); } -static void config_nb_syn_ptr_adj(device_t dev) { +static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ + /* adjust FIFO between nb and core clocks to max allowed + values (min latency) */ + u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; + u8 nbSynPtrAdj; + if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) + || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { + nbSynPtrAdj = 5; + } else { + nbSynPtrAdj = 6; + } + u32 dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); - } static void config_acpi_pwr_state_ctrl_regs(device_t dev) { @@ -364,7 +376,7 @@ static void prep_fid_change(void) config_clk_power_ctrl_reg0(i,cpuRev,procPkg); config_power_ctrl_misc_reg(dev,cpuRev,procPkg); - config_nb_syn_ptr_adj(dev); + config_nb_syn_ptr_adj(dev,cpuRev); config_acpi_pwr_state_ctrl_regs(dev); diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 2ef46ffe9e..3907208290 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -181,6 +181,8 @@ #define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/ #define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */ #define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */ +#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */ +#define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */ #define PRCT_INFO 0x1fc /* Product Info Register */ #define UNI_NB_FID_BIT 2 /* UniNbFid bit position */ @@ -224,6 +226,10 @@ /* F4x1F4 Northbridge P-state spec register */ #define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */ +/* F3x1F0 Product Information Register */ +#define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */ + + #define NM_PS_REG 5 /* number of P-state MSR registers */ /* sFidVidInit.outFlags defines */ |