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authorShelley Chen <shchen@chromium.org>2017-06-29 11:31:16 -0700
committerAaron Durbin <adurbin@chromium.org>2017-07-14 22:47:25 +0000
commit20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 (patch)
tree4f53314fef60d9a75fea39ce13e76bd85e3f9c5b /src
parent2a7fbea3f14cae2119816c5a28c455f45c75650f (diff)
downloadcoreboot-20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1.tar.xz
soc/intel/skylake: Set PsysPL2 MSR
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/skylake/cpu.c17
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h1
3 files changed, 20 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b4f6545c36..67a6783186 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -97,6 +97,9 @@ struct soc_intel_skylake_config {
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
+ /* SysPL2 Value in Watts */
+ u32 tdp_psyspl2;
+
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 7f455e0d59..1a081915a2 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -160,10 +160,11 @@ void set_power_limits(u8 power_limit_1_time)
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT;
- /* Set short term power limit to 1.25 * TDP */
+ /* Set short term power limit to 1.25 * TDP if no config given */
limit.hi = 0;
tdp_pl2 = (conf->tdp_pl2_override == 0) ?
(tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
+ printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
@@ -175,6 +176,20 @@ void set_power_limits(u8 power_limit_1_time)
MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
+ /* Set PsysPl2 */
+ if (conf->tdp_psyspl2) {
+ limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
+ limit.hi = 0;
+ printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
+ conf->tdp_psyspl2);
+ limit.hi |= (conf->tdp_psyspl2 * power_unit) &
+ PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_CLAMP;
+ limit.hi |= PKG_POWER_LIMIT_EN;
+
+ wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
+ }
+
/* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 81b6cc9de1..4ff4ad2d49 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -37,5 +37,6 @@
#define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
+#define MSR_PLATFORM_POWER_LIMIT 0x65c
#endif