diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-23 16:24:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 16:27:52 +0000 |
| commit | 21cdf0de086e045988b93b6030f8faa5127f5cdf (patch) | |
| tree | 99a0b31c112d7385a00cf6f264ebede643fff9ea /src | |
| parent | 4b84a2c8a2db0998406abd5ed304814a5f2110a3 (diff) | |
| download | coreboot-21cdf0de086e045988b93b6030f8faa5127f5cdf.tar.xz | |
soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Add a Kconfig symbol for including the PCIe MMCONF setup function in the
build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the
southbridges call enable_pci_mmconf(), but don't select
SOC_AMD_COMMON_BLOCK_PCI.
Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47878
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/pci/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pci/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/Kconfig | 1 |
5 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 74ea69784d..a59d87eb54 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -1,6 +1,14 @@ config SOC_AMD_COMMON_BLOCK_PCI bool default n + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF help This option builds functions used to program PCI interrupt routing, both PIC and APIC modes. + +config SOC_AMD_COMMON_BLOCK_PCI_MMCONF + bool + default n + help + Selecting this option adds the AMD-common enable_pci_mmconf function + to the build. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 1fed96e45a..78453d464f 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,8 +1,11 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -# FIXME: This gets added when CONFIG_SOC_AMD_COMMON is set, which is a bit unexpected. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) + bootblock-y += amd_pci_mmconf.c verstage_x86-y += amd_pci_mmconf.c romstage-y += amd_pci_mmconf.c postcar-y += amd_pci_mmconf.c ramstage-y += amd_pci_mmconf.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b755fe1811..d0fbc49a36 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 96737cfbb6..ecfc1e1c5f 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 config ENABLE_IDE_COMBINED_MODE diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 89dcad6086..c87d7a0904 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex |