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authorJustin TerAvest <teravest@chromium.org>2018-03-15 16:28:57 -0600
committerMartin Roth <martinroth@google.com>2018-03-19 15:09:10 +0000
commit22595f6e45a5f97bdeb182ef809a5c9a1815052d (patch)
treec0ba15154f1f112de3443e1f70b76237d3bfe35f /src
parent04ccd5f9b5006363dac228379057d0b48ed8768b (diff)
downloadcoreboot-22595f6e45a5f97bdeb182ef809a5c9a1815052d.tar.xz
mb/google/octopus: Fix GPIO config for DRAM_IDs
The GPIO pad configurations for GPIO68-71 are incorrectly configured as outputs. This change corrects them to be inputs. BUG=b:74932341 TEST=None Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25217 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/gpio.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index 6b71a09b78..1570223b6e 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -92,10 +92,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */
- PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS0 */
- PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS1 */
- PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS2 */
- PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_RXD */
+ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
+ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
+ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */
+ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */