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authorKevin Chiu <kevin.chiu.17802@gmail.com>2021-04-14 10:37:08 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-15 07:31:08 +0000
commit24141482206f49111c7c9cd73ef3324d1962288a (patch)
treea96f3ae153afca3cbc178be5e386185fe6115d92 /src
parentfde6b65b5235cc4ddda5c215056a09aad240fa0e (diff)
downloadcoreboot-24141482206f49111c7c9cd73ef3324d1962288a.tar.xz
mb/google/zork: fine tune stamp_boost parameter for dirinboz
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:175364713,b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/dirinboz/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
index 7139ac8ec2..5675487c70 100644
--- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
@@ -12,7 +12,7 @@ chip soc/amd/picasso
register "slow_ppt_limit_mW" = "6000"
register "fast_ppt_limit_mW" = "9000"
register "slow_ppt_time_constant_s" = "5"
- register "stapm_time_constant_s" = "1640"
+ register "stapm_time_constant_s" = "1400"
register "sustained_power_limit_mW" = "4800"
register "telemetry_vddcr_vdd_slope_mA" = "41322"