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authordavid <david_wu@quantatw.com>2015-12-06 16:48:58 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-16 12:01:00 +0100
commit2672ee3e3a021619edba8db7ebacdc9a34654c06 (patch)
treebca525b5379ce4b9d01c7c112393e925cf277279 /src
parent0ab8e00aebd360b5b99690de4948004dc2738770 (diff)
downloadcoreboot-2672ee3e3a021619edba8db7ebacdc9a34654c06.tar.xz
google/lars: Add new configuration parameters
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313309/ BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3 Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/lars/devicetree.cb30
1 files changed, 17 insertions, 13 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index d85d25c61d..958c333a46 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/skylake
# Enable deep Sx states
- register "deep_s3_enable" = "0"
register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
@@ -20,28 +19,33 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
- register "ProbelessTrace" = "0"
- register "EnableLan" = "0"
- register "EnableSata" = "0"
- register "SataSalpSupport" = "0"
- register "SataMode" = "0"
- register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
- register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
- register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
- register "IshEnable" = "0"
- register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "WakeConfigWolEnableOverride" = "0x01"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"