summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-23 20:40:53 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-09 12:42:56 +0100
commit26929bd71af443ae2a7080a6bd2bd9b8054a362c (patch)
treea5483173de3f60b5571ac621627cbd223233400c /src
parent171d1a5979800e3f8d3fc4c55fe08d50367f1dba (diff)
downloadcoreboot-26929bd71af443ae2a7080a6bd2bd9b8054a362c.tar.xz
AGESA: Fix SSE regression and align stack early
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. Fixes regression with new toolchain using GCC-6.3 and ec0a393 console: Enable printk for ENV_LIBAGESA For some builds, the above-mentioned commit emitted SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/agesa/cache_as_ram.inc8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 24db6001ea..c0a69ec74a 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -63,6 +63,9 @@ cache_as_ram_setup:
AMD_ENABLE_STACK
+ /* Align the stack. */
+ and $0xFFFFFFF0, %esp
+
#ifdef __x86_64__
/* switch to 64 bit long mode */
mov %esi, %ecx
@@ -111,8 +114,6 @@ cache_as_ram_setup:
/* Pass the BIST result */
cvtsd2si %xmm0, %edi
- /* align the stack */
- and $0xFFFFFFF0, %esp
.code64
call cache_as_ram_main
@@ -126,6 +127,9 @@ cache_as_ram_setup:
/* Restore the cpu_init_detected */
cvtsd2si %xmm1, %ebx
+ /* Must maintain 16-byte stack alignment here. */
+ pushl $0x0
+ pushl $0x0
pushl %ebx /* init detected */
pushl %edx /* bist */
call cache_as_ram_main