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authorDavid Hendricks <dhendrix@chromium.org>2013-03-28 19:05:29 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-29 22:24:35 +0100
commit26e8f2fe0125cc6e7727d024bf4bfbd6231c8b27 (patch)
tree55b4d6340aa9bf63325cac815783e3c2fec4dcf3 /src
parentc01d1380138e807fa941976d9f102fb1b200ad01 (diff)
downloadcoreboot-26e8f2fe0125cc6e7727d024bf4bfbd6231c8b27.tar.xz
snow: explicitly configure L2 cache
This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2950 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/snow/ramstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 1751a1b8aa..908162914f 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -21,6 +21,7 @@
#include <cbmem.h>
#include <arch/exception.h>
#include <cpu/samsung/exynos5250/clk.h>
+#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h>
#include <arch/cache.h>
@@ -45,6 +46,7 @@ void main(void)
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
+ exynos5250_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);