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authorChris Morgan <macromorgan@hotmail.com>2020-02-05 10:51:46 -0600
committerFelix Held <felix-coreboot@felixheld.de>2020-02-06 18:10:43 +0000
commit2806ec971e11cccee86927ddde6ace3a34319cfb (patch)
tree64f05cd1efab2019b4b7dada67033e10f35fef87 /src
parentfaa1118fc7d6d80d9c37bab8b9330325d8157466 (diff)
downloadcoreboot-2806ec971e11cccee86927ddde6ace3a34319cfb.tar.xz
nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)
The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board to enable the dGPU. Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/haswell/early_init.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 666bda28f8..6aad4a381f 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -101,7 +101,7 @@ static void start_peg2_link_training(const pci_devfn_t dev)
}
pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
- printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev));
+ printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
/*
* The PEG device is hidden while the MRC runs. This is because the
@@ -110,8 +110,8 @@ static void start_peg2_link_training(const pci_devfn_t dev)
* to these configurations.
*/
pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0);
- peg_hidden[PCI_FUNC(dev)] = true;
- printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev));
+ peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+ printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
}
void haswell_unhide_peg(void)