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authorFelix Held <felix-coreboot@felixheld.de>2021-02-17 22:16:40 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-19 13:19:24 +0000
commit285dd6ec3a8529d2b91eb657e85007be6a3397b6 (patch)
treee706223e60933d3b883d1d1930ba738b1d30f7bd /src
parent82d16b150ce3287f4e9f33e86bdde32bc455b193 (diff)
downloadcoreboot-285dd6ec3a8529d2b91eb657e85007be6a3397b6.tar.xz
soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/include/cpu/amd/msr.h1
-rw-r--r--src/soc/amd/common/block/include/amdblocks/psp.h2
-rw-r--r--src/soc/amd/common/block/psp/psp_gen2.c1
-rw-r--r--src/soc/amd/stoneyridge/cpu.c2
-rw-r--r--src/soc/amd/stoneyridge/psp.c1
5 files changed, 4 insertions, 3 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 78676de266..4e372c41b8 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -78,6 +78,7 @@
#define LS_CFG2_MSR 0xC001102D
#define IBS_OP_DATA3_MSR 0xC0011037
#define S3_RESUME_EIP_MSR 0xC00110E0
+#define MSR_PSP_ADDR 0xc00110a2
#define MSR_PATCH_LEVEL 0x0000008B
#define CORE_PERF_BOOST_CTRL 0x15c
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 9d56d6beee..8cd8236706 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -3,8 +3,6 @@
#ifndef AMD_BLOCK_PSP_H
#define AMD_BLOCK_PSP_H
-#define MSR_PSP_ADDR 0xc00110a2
-
/* Get the mailbox base address - specific to family of device. */
void *soc_get_mbox_address(void);
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index ca84057453..95adce40d2 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
+#include <cpu/amd/msr.h>
#include <cpu/x86/msr.h>
#include <device/mmio.h>
#include <timer.h>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index badea8bb90..17fd9b97bb 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/smm.h>
+#include <cpu/amd/msr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
@@ -15,7 +16,6 @@
#include <soc/smi.h>
#include <soc/iomap.h>
#include <console/console.h>
-#include <amdblocks/psp.h>
/*
* MP and SMM loading initialization.
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index 69db08dfc3..cd14d7bf69 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -3,6 +3,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
+#include <cpu/amd/msr.h>
#include <cpu/x86/msr.h>
#include <soc/pci_devs.h>
#include <soc/northbridge.h>