diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-13 17:04:02 -0700 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2011-10-15 13:40:17 +0200 |
| commit | 328a694a3f2055c5e6a88ae51c9a8eefb61fd11c (patch) | |
| tree | b738e9265f3e2d86dd66d995a5f949982982394d /src | |
| parent | ab87254b6130d74f080e2c5ee9abb4570560e6a0 (diff) | |
| download | coreboot-328a694a3f2055c5e6a88ae51c9a8eefb61fd11c.tar.xz | |
AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/amdk8/early_ht.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/incoherent_ht.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.c | 2 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index bf80ef833e..2ecc0d0d60 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -16,8 +16,8 @@ static void enumerate_ht_chain(void) device_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid; - uint8_t real_last_pos; + unsigned real_last_unitid = 0; + uint8_t real_last_pos = 0; int ht_dev_num = 0; // except host_bridge uint8_t end_used = 0; #endif diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 4d0d0259f6..a14adac70d 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -305,8 +305,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid; - uint8_t real_last_pos; + unsigned real_last_unitid = 0; + uint8_t real_last_pos = 0; int ht_dev_num = 0; uint8_t end_used = 0; #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1191536234..1faed5a2e9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1353,7 +1353,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, u16 tCKproposed16x; u8 CLactual, CLdesired, CLT_Fail; - u8 smbaddr, byte, bytex; + u8 smbaddr, byte = 0, bytex = 0; CASLatLow = 0xFF; CASLatHigh = 0xFF; @@ -2768,7 +2768,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, u8 dct, u32 dev, u32 index_reg) { - u8 Smallest, Largest; + u8 Smallest = 0, Largest = 0; u32 val; u8 byte, bytex; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 54fdedf08c..3e1b13d01f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -849,7 +849,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat u32 value; u8 j; u32 value_test; - u32 value_r, value_r_test; + u32 value_r = 0, value_r_test = 0; u8 pattern, channel, BeatCnt; struct DCTStatStruc *ptrAddr; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index b8c7d04822..cf6d2dfb1a 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24, romstrap2; - msr_t pcie_mmio_save; + msr_t pcie_mmio_save = { 0, 0 }; volatile u32 * strap; // disable processor pcie mmio, if enabled |