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| author | Frans Hendriks <fhendriks@eltan.com> | 2020-11-19 15:45:43 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:17:22 +0000 |
| commit | 335eb1219c73032eee92462f76d508233fb97b55 (patch) | |
| tree | c66e3c5d42eccc96a99153efc79fa6b8ca278483 /src | |
| parent | f752fc654610cb8dd481a9b735b495e2109610e0 (diff) | |
| download | coreboot-335eb1219c73032eee92462f76d508233fb97b55.tar.xz | |
src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
Whole car region is cleared, while only small part needs to be done.
Clear .bss area only
Tested on Facebook FBG1701
Change-Id: I021c2f7d3531c553015fde98d155915f897b434d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3be9eb92df..b5b47ce9a6 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -145,14 +145,13 @@ CAR_init_done: * mm1: high 32-bits of TSC value */ - /* coreboot assumes stack/heap region will be zero */ + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl /* Need to align stack to 16 bytes at call instruction. Account for |