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authorJustin TerAvest <teravest@chromium.org>2018-01-26 15:19:08 -0700
committerMartin Roth <martinroth@google.com>2018-01-29 16:11:38 +0000
commit339e771055ff8f7d1f9652cb4d68be6b15e97016 (patch)
treedbb05176e0f721fc02349e054ef925f948cb0a6d /src
parent763e493602cb8b203dc45f32f829f1c57872380d (diff)
downloadcoreboot-339e771055ff8f7d1f9652cb4d68be6b15e97016.tar.xz
mb/google/kahlee: Fix I2C bus 1 timing for Grunt
I measured the rise and fall times for I2C bus 1 from userspace manually, using "i2cdetect 1" called from userspace and an oscilloscope. This commit fixes the values there to reflect reality. BUG=b:72442912,b:70232394 Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23459 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kahlee/variants/grunt/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
index 977e32d1db..d2453a1e67 100644
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -28,11 +28,11 @@ chip soc/amd/stoneyridge
.fall_time_ns = 52,
}"
- # TODO(teravest): Fix speeds here.
+ # Enable I2C1 for H1 at 400kHz
register "i2c[1]" = "{
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 104,
- .fall_time_ns = 52,
+ .rise_time_ns = 84,
+ .fall_time_ns = 4,
}"
# TODO(teravest): Fix speeds here.