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authorAaron Durbin <adurbin@chromium.org>2016-07-14 00:56:58 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:36:12 +0200
commit38613d079d9960111dbc334800c77d10b6c28132 (patch)
tree89fe8a0fe34842e7dcdc15b6230a8e9585aedb14 /src
parent1a755605996e2b46af0245c169c8e96312bcdb80 (diff)
downloadcoreboot-38613d079d9960111dbc334800c77d10b6c28132.tar.xz
soc/intel/skylake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15688 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/pmutil.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 67ca9bdc88..0f747348a4 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -24,6 +24,7 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <halt.h>
#include <stdlib.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -430,3 +431,9 @@ uint16_t pmc_tco_regs(void)
return reg16;
}
+
+void poweroff(void)
+{
+ enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ halt();
+}