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authorArindam Roy <arindam.roy@intel.com>2015-12-04 16:46:24 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-15 11:56:34 +0100
commit3b43fa90866ade5805e95ea522aa0f43820550e8 (patch)
treefa1c6cbb452aa7fc3ff028d6f8841caedd952a9d /src
parentda6666b0501dbe08fe39e30086a77090d889ff01 (diff)
downloadcoreboot-3b43fa90866ade5805e95ea522aa0f43820550e8.tar.xz
intel/kunimitsu: Correct the output for crossystem wpsw_boot
The write protect GPIO is not being configured early enough. This is leading to coreboot reading incorrect value, and writing the incorrect value in vboot shared file. This is leading to "crossystem wpsw_boot" always returning 0 even with the write protect screw in place during boot. BUG=chrome-os-partner:48292 BRANCH=None TEST=Boot with the write protect screw in place. Issue crossystem wpsw_boot. It should show 1. Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81 Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316009 Original-Commit-Ready: Arindam Roy <rarindam@gmail.com> Original-Tested-by: Arindam Roy <rarindam@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12952 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rwxr-xr-xsrc/mainboard/intel/kunimitsu/gpio.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index cfec92e75a..f02732603c 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -231,6 +231,7 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
};
#endif