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author | Angel Pons <th3fanbus@gmail.com> | 2020-09-25 00:37:06 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:38:08 +0000 |
commit | 3b8b00fd39b3dbbf42b41a018e2bdf264479fc97 (patch) | |
tree | 7a607f6f71ee8e6a5219ffd27e38dafe665bafae /src | |
parent | d5689dd289d1108249d8c7ed779ae62fbd8963bf (diff) | |
download | coreboot-3b8b00fd39b3dbbf42b41a018e2bdf264479fc97.tar.xz |
soc/intel/broadwell/smi.c: Drop unused functions
These aren't used anywhere, so get rid of them.
Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/soc/intel/broadwell/smi.c | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 317da0cc2d..d7704fd8fa 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -54,35 +54,3 @@ void global_smi_enable(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -static void __unused southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static void __unused southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} |