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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-05-09 21:15:13 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-05-09 21:15:13 +0000
commit3d5bb236aa6147ce24d9618f2d482e76eefc58c6 (patch)
treee6769779f4f549224c3c39704a4fa98b12c335a4 /src
parentbf9e5384d7c25be41d008d29c38b24155676acc0 (diff)
downloadcoreboot-3d5bb236aa6147ce24d9618f2d482e76eefc58c6.tar.xz
Move includes to where they are needed. This allows to simplify
romstage.c files in mainboards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/arch/i386/include/stddef.h2
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c1
-rw-r--r--src/cpu/amd/model_10xxx/defaults.h2
-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c6
-rw-r--r--src/cpu/amd/quadcore/quadcore.c1
-rw-r--r--src/include/cpu/amd/model_10xxx_msr.h2
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.c3
-rw-r--r--src/northbridge/amd/amdmct/mct/mctmtr_d.c1
-rw-r--r--src/superio/smsc/smscsuperio/smscsuperio_early_serial.c1
9 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/i386/include/stddef.h b/src/arch/i386/include/stddef.h
index e4fc019c87..6583cc62ef 100644
--- a/src/arch/i386/include/stddef.h
+++ b/src/arch/i386/include/stddef.h
@@ -8,7 +8,9 @@ typedef long ssize_t;
typedef int wchar_t;
typedef unsigned int wint_t;
+#ifndef NULL
#define NULL ((void *)0)
+#endif
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 24ea8da5e6..58d38cd603 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,6 +1,7 @@
/* 2005.6 by yhlu
* 2006.3 yhlu add copy data from CAR to ram
*/
+#include <string.h>
#include <arch/stages.h>
#include "cpu/amd/car/disable_cache_as_ram.c"
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 98918ec312..78c46d4eaf 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <cpu/amd/mtrr.h>
/*
* Default MSR and errata settings.
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 3a86be296f..a64cdd8874 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -18,6 +18,12 @@
*/
#include "defaults.h"
+#include <stdlib.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/porting.h>
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef SET_FIDVID
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index d66f56c881..142a270125 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h
index a774125cb0..f497eb3a82 100644
--- a/src/include/cpu/amd/model_10xxx_msr.h
+++ b/src/include/cpu/amd/model_10xxx_msr.h
@@ -20,6 +20,8 @@
#ifndef CPU_AMD_MODEL_10XXX_MSR_H
#define CPU_AMD_MODEL_10XXX_MSR_H
+#include <cpu/x86/msr.h>
+
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
#define LS_CFG_MSR 0xC0011020
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index f02ce44f80..38733c9863 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
/*----------------------------------------------------------------------------
* TYPEDEFS, DEFINITIONS AND MACROS
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index 76cf9806af..64500f0d58 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -19,6 +19,7 @@
#include "mct_d.h"
+#include <cpu/amd/mtrr.h>
static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);
static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);
diff --git a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
index 28022b649e..de2e891742 100644
--- a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
+++ b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
@@ -19,6 +19,7 @@
*/
#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
/* All known/supported SMSC Super I/Os have the same logical device IDs
* for the serial ports (COM1, COM2).