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authorFelix Singer <felix.singer@secunet.com>2020-09-07 13:57:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-02 06:30:32 +0000
commit3d9fa08bf128ecef5aa795c04443f1cd9a76603d (patch)
treedbaa9d1bf6dcc8382272af0a8036fe15cf4c9379 /src
parentd7511f805453982ad23173fbba5f1110e6d5fa9c (diff)
downloadcoreboot-3d9fa08bf128ecef5aa795c04443f1cd9a76603d.tar.xz
device: Rework bus master option
As an intermediate step for CB:45150, add an additional Kconfig option which is used to configure bus mastering for any devices and use PCI_ALLOW_BUS_MASTER to allow coreboot setting the bus mastering bit in general. Change-Id: I33b37a79022007a16e97350db61575b63fa8256b Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45149 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/device/Kconfig11
-rw-r--r--src/include/device/pci.h2
2 files changed, 12 insertions, 1 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index cbe970f170..777f3f50d3 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -532,6 +532,17 @@ config PCI_ALLOW_BUS_MASTER
instance, for libpayload based payloads as the drivers don't enable
bus mastering for PCI bridges.
+if PCI_ALLOW_BUS_MASTER
+
+config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
+ bool "Any devices"
+ default y
+ help
+ Allow coreboot to enable PCI bus mastering for any device. The actual
+ selection of devices depends on the various PCI drivers in coreboot.
+
+endif # PCI_ALLOW_BUS_MASTER
+
endif # PCI
if PCIEXP_PLUGIN_SUPPORT
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 58f5904996..777f030355 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -144,7 +144,7 @@ void pci_dev_request_bus_master(pci_devfn_t dev)
void pci_dev_request_bus_master(struct device *dev)
#endif /* ENV_PCI_SIMPLE_DEVICE */
{
- if (CONFIG(PCI_ALLOW_BUS_MASTER))
+ if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}