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| author | Aaron Durbin <adurbin@chromium.org> | 2017-12-14 16:14:39 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-15 23:35:16 +0000 |
| commit | 410f3b402a29af09070520bd13ea90e75ae2f5ec (patch) | |
| tree | ca0f641730ee51aeb4f0ce14e81ff18b41bc9b89 /src | |
| parent | 10d65b06aebbd857759c278a18c7e9e0ba70ee6c (diff) | |
| download | coreboot-410f3b402a29af09070520bd13ea90e75ae2f5ec.tar.xz | |
soc/intel/common/nvm: utilize spi_flash_ctrlr_protect_region()
Now that there is spi flash controller flash protection use that API
so the spi_flash_protect() API can be sunsetted since it was isolated
within the Intel code base.
BUG=b:69614064
Change-Id: I3908d0e3105b0ef9a0fbf4fc9426ac1be067f648
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/nvm.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index b7e0f4e7ac..61b7a65991 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -22,7 +22,6 @@ #include <spi_flash.h> #include <vendorcode/google/chromeos/chromeos.h> #include "nvm.h" -#include "spi_flash.h" /* Read flash status register to determine if write protect is active */ int nvm_is_write_protected(void) @@ -62,5 +61,5 @@ int nvm_protect(const struct region *r) if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) return 0; - return spi_flash_protect(region_offset(r), region_sz(r)); + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r); } |