diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 20:17:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-25 10:06:34 +0000 |
| commit | 437c2baac4f30e86c5fa7c6bf674eb269029456b (patch) | |
| tree | 1e7b5310fc4e0ab8e30fded437e23f8e10ebe47c /src | |
| parent | 57a2a3ba935b4df4686fdcfba3ae7fc2218e20f3 (diff) | |
| download | coreboot-437c2baac4f30e86c5fa7c6bf674eb269029456b.tar.xz | |
soc/intel/{skl,cnl}: Uniformize romstage.h whitespace
Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/romstage.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/romstage.h | 9 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index ae9aa6074b..3772db4bc1 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -6,7 +6,6 @@ #include <fsp/api.h> void mainboard_memory_init_params(FSPM_UPD *mupd); - void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index b9eea98637..fe8bc21907 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -11,9 +11,10 @@ void romstage_pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { - BOARD_TYPE_MOBILE = 0, - BOARD_TYPE_DESKTOP = 1, - BOARD_TYPE_ULT_ULX = 5, - BOARD_TYPE_SERVER = 7 + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 }; + #endif /* _SOC_ROMSTAGE_H_ */ |