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authordavid <david_wu@quantatw.com>2015-12-09 13:12:21 +0800
committerMartin Roth <martinroth@google.com>2016-01-17 00:04:00 +0100
commit441be59ae0528a62db9d15e822ca3d739ad71dd1 (patch)
treedde9c96800b33f37c83695c7ea698c245408e14f /src
parentd91b1dfabbeb20080cd5b70fbb0e82c6cf839a04 (diff)
downloadcoreboot-441be59ae0528a62db9d15e822ca3d739ad71dd1.tar.xz
google/lars: Remove/Disable Wake on lan
Remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and boot on lars Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9 Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317080 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/lars/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 958c333a46..f08c67e9ea 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -29,7 +29,6 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
- register "WakeConfigWolEnableOverride" = "0x01"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s