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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 15:01:43 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:38:22 +0000 |
| commit | 4537332d64a66fac1c1d6b615838c54d33fdefab (patch) | |
| tree | f39f47be788947bfd609396643f27f7aabcd3697 /src | |
| parent | 1550469234618ec2899ca17e1eda1e0611cddb22 (diff) | |
| download | coreboot-4537332d64a66fac1c1d6b615838c54d33fdefab.tar.xz | |
northbridge/intel/gm45/bootblock.c: Remove repeated word
Change-Id: Ie3bfdb27aa7c981a500e82b6a6958576e0048bcd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index a0e8fc0631..2e41981e75 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -12,7 +12,7 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use + * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the |