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authorElyes HAOUAS <ehaouas@noos.fr>2016-06-15 19:05:11 +0200
committerMartin Roth <martinroth@google.com>2016-06-24 18:08:04 +0200
commit46bfce335337a11a9b48c496672bd6020e8dbaeb (patch)
treea759a164557a157d100c8059668626209d9344b4 /src
parenta1850bafbffd147bd5aad8b2a6463f40cc28ddec (diff)
downloadcoreboot-46bfce335337a11a9b48c496672bd6020e8dbaeb.tar.xz
spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10. Change-Id: I0112a85f557826b629109e212dbbc752aeda305d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/spd.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/spd.h b/src/include/spd.h
index 7aaf4dd896..7c4a2e3801 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -125,6 +125,7 @@ enum spd_memory_type {
#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
+#define SPD_VOLTAGE_SSTL1 5 /* SSTL 1.8 */
/* SPD_DIMM_CONFIG_TYPE values. */
#define ERROR_SCHEME_NONE 0