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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-12-27 15:21:58 +0100
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-27 19:49:46 +0100
commit475e1b9095d15c02daa6bf41a88d5e1245ed10be (patch)
tree05b8f5cd6d04d631d723e0df29cf554adc414760 /src
parentba6c2663ed45b6bd82e324ede4e903176181dcfa (diff)
downloadcoreboot-475e1b9095d15c02daa6bf41a88d5e1245ed10be.tar.xz
via: Write »access« without »m« at end
The comment was copied around so fix all occurrences using the following command. $ git grep -l accessm | xargs sed -i 's/accessm/access/g' Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/via/epia-m700/romstage.c2
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c2
-rw-r--r--src/southbridge/via/vt8237r/early_smbus.c4
-rw-r--r--src/southbridge/via/vt8237r/lpc.c2
4 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 1936052537..fda1bb06dd 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -67,7 +67,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
tmp = inw(VX800_ACPI_IO_BASE + 0x04);
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index b629137d95..2ab3e64659 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -54,7 +54,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
tmp = inw(VX800_ACPI_IO_BASE + 0x04);
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index b087a471b4..b41e1ad925 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -274,7 +274,7 @@ void vt8237_sb_enable_fid_vid(void)
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
/* chipset-specific parts */
@@ -342,7 +342,7 @@ static int acpi_is_wakeup_early(void) {
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index d8251a08fa..4949de6560 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -215,7 +215,7 @@ static void setup_pm(device_t dev)
/* Disable GP3 timer. */
pci_write_config8(dev, 0x98, 0);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
/* Clear status events. */