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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2019-07-09 13:30:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:01:59 +0000 |
| commit | 489c722dccbf7b57cab6f1b0e17a14e889d9da4e (patch) | |
| tree | ddd1da46f2159e14d42cafdd86631b3aa01e4c16 /src | |
| parent | 145748bf25b658da1d2951201413ba9b0c68a266 (diff) | |
| download | coreboot-489c722dccbf7b57cab6f1b0e17a14e889d9da4e.tar.xz | |
mb/google/hatch: Enable LPIT inclusion in DSDT
Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/dsdt.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 243c6270e2..87e98ea925 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -51,6 +51,9 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/cannonlake/acpi/sleepstates.asl> + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { |