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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-22 07:52:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-23 17:16:41 +0000 |
| commit | 4b2c12f0937fe39c12cb56e1787e15e8ac51aa2c (patch) | |
| tree | 92a5a40e00bbca64a893b860695a7a9eea3b751f /src | |
| parent | 802f43d67fc12c738325c860c5547e33141cff66 (diff) | |
| download | coreboot-4b2c12f0937fe39c12cb56e1787e15e8ac51aa2c.tar.xz | |
src/soc/intel/braswell/southcluster.c: Replace fixed values by defines
The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29788
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ae4b8c5057..0c88004323 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -126,10 +126,10 @@ static void sc_add_io_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); /* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } static void sc_read_resources(struct device *dev) |